Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	700708	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5772953

1

T17

11

T18

12

T19

11

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1722847	1			T17	10		T18	20		T19	17
values[0x0]	2204566	1			T17	5		T18	8		T19	6
values[0x1]	2546248	1			T17	6		T18	12		T19	5

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	350982	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6122679

1

T17

13

T18

13

T19

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23858	1			T23	1		T44	1		T22	8
valid_sources[0x01]	24220	1			T17	1		T61	16		T23	4
valid_sources[0x02]	25472	1			T23	3		T44	1		T46	2
valid_sources[0x03]	24821	1			T23	2		T22	7		T26	7
valid_sources[0x04]	25323	1			T23	2		T44	1		T45	1
valid_sources[0x05]	25777	1			T20	1		T23	2		T131	1
valid_sources[0x06]	23849	1			T20	1		T23	2		T44	1
valid_sources[0x07]	25639	1			T23	6		T205	1		T241	10
valid_sources[0x08]	23908	1			T43	4		T23	3		T44	2
valid_sources[0x09]	25550	1			T43	1		T23	1		T46	1
valid_sources[0x0a]	25814	1			T17	1		T20	1		T45	1
valid_sources[0x0b]	25269	1			T27	1		T23	2		T44	1
valid_sources[0x0c]	25450	1			T20	1		T23	1		T44	2
valid_sources[0x0d]	25637	1			T20	1		T23	2		T46	2
valid_sources[0x0e]	26044	1			T23	1		T44	1		T46	3
valid_sources[0x0f]	24231	1			T20	1		T43	2		T23	5
valid_sources[0x10]	26301	1			T20	2		T22	3		T26	1
valid_sources[0x11]	25091	1			T23	3		T46	1		T126	1
valid_sources[0x12]	25040	1			T17	1		T23	3		T44	1
valid_sources[0x13]	26227	1			T20	1		T23	2		T46	5
valid_sources[0x14]	26429	1			T23	1		T44	1		T21	1
valid_sources[0x15]	27403	1			T23	1		T131	1		T45	1
valid_sources[0x16]	24521	1			T20	1		T23	1		T44	1
valid_sources[0x17]	25951	1			T23	2		T127	5		T241	4
valid_sources[0x18]	26490	1			T23	2		T46	3		T22	2
valid_sources[0x19]	24007	1			T23	2		T22	2		T126	5
valid_sources[0x1a]	27228	1			T23	2		T131	1		T22	1
valid_sources[0x1b]	26584	1			T23	4		T44	1		T22	3
valid_sources[0x1c]	26580	1			T23	1		T44	1		T22	4
valid_sources[0x1d]	26122	1			T23	1		T44	1		T22	3
valid_sources[0x1e]	25155	1			T17	3		T23	2		T26	4
valid_sources[0x1f]	26094	1			T61	1		T23	1		T131	1
valid_sources[0x20]	23757	1			T23	1		T22	11		T26	3
valid_sources[0x21]	24480	1			T44	5		T45	1		T46	6
valid_sources[0x22]	24961	1			T23	1		T26	2		T126	4
valid_sources[0x23]	26425	1			T44	1		T22	4		T26	2
valid_sources[0x24]	25033	1			T17	1		T23	4		T22	3
valid_sources[0x25]	26569	1			T23	5		T22	4		T126	3
valid_sources[0x26]	25516	1			T23	1		T22	2		T163	1
valid_sources[0x27]	27453	1			T23	3		T22	4		T126	1
valid_sources[0x28]	25690	1			T23	1		T44	1		T22	4
valid_sources[0x29]	24782	1			T61	1		T23	3		T45	2
valid_sources[0x2a]	26089	1			T23	1		T46	1		T22	6
valid_sources[0x2b]	23353	1			T20	1		T23	2		T46	1
valid_sources[0x2c]	25448	1			T44	1		T46	3		T22	1
valid_sources[0x2d]	25922	1			T23	2		T44	2		T46	4
valid_sources[0x2e]	26029	1			T23	2		T45	1		T46	2
valid_sources[0x2f]	25947	1			T43	2		T23	1		T21	1
valid_sources[0x30]	24158	1			T23	5		T44	1		T126	2
valid_sources[0x31]	23793	1			T46	4		T26	1		T242	3
valid_sources[0x32]	24597	1			T23	1		T44	2		T22	1
valid_sources[0x33]	25933	1			T20	1		T23	2		T22	3
valid_sources[0x34]	24278	1			T22	2		T26	7		T126	3
valid_sources[0x35]	25984	1			T18	2		T43	1		T23	2
valid_sources[0x36]	26294	1			T43	1		T23	3		T21	2
valid_sources[0x37]	25040	1			T23	1		T22	2		T26	5
valid_sources[0x38]	24214	1			T23	7		T46	16		T22	2
valid_sources[0x39]	24549	1			T23	2		T45	1		T21	1
valid_sources[0x3a]	23863	1			T26	1		T155	2		T127	1
valid_sources[0x3b]	25420	1			T23	2		T22	3		T26	1
valid_sources[0x3c]	25013	1			T23	2		T44	1		T22	1
valid_sources[0x3d]	25643	1			T20	2		T126	4		T241	13
valid_sources[0x3e]	26470	1			T17	2		T44	1		T131	1
valid_sources[0x3f]	24667	1			T23	1		T44	1		T22	9
valid_sources[0x40]	25717	1			T23	3		T44	1		T45	1
valid_sources[0x41]	25294	1			T20	1		T126	1		T124	19
valid_sources[0x42]	26920	1			T23	2		T44	1		T45	1
valid_sources[0x43]	24312	1			T20	1		T23	2		T44	1
valid_sources[0x44]	24617	1			T23	2		T126	6		T241	8
valid_sources[0x45]	22852	1			T23	3		T22	3		T204	1
valid_sources[0x46]	25283	1			T23	1		T44	2		T131	3
valid_sources[0x47]	26703	1			T23	1		T44	1		T21	1
valid_sources[0x48]	24173	1			T23	3		T22	1		T26	6
valid_sources[0x49]	25612	1			T23	3		T45	1		T22	2
valid_sources[0x4a]	26324	1			T23	3		T44	1		T21	1
valid_sources[0x4b]	25581	1			T23	2		T45	1		T21	1
valid_sources[0x4c]	25200	1			T23	4		T44	1		T26	9
valid_sources[0x4d]	24731	1			T23	3		T44	1		T22	1
valid_sources[0x4e]	25132	1			T23	3		T44	1		T131	1
valid_sources[0x4f]	25335	1			T20	1		T23	2		T22	4
valid_sources[0x50]	26443	1			T22	4		T26	2		T126	2
valid_sources[0x51]	23933	1			T44	2		T163	12		T26	14
valid_sources[0x52]	24346	1			T23	6		T46	6		T22	4
valid_sources[0x53]	25798	1			T21	6		T46	4		T22	1
valid_sources[0x54]	26934	1			T20	1		T23	3		T44	1
valid_sources[0x55]	24192	1			T23	1		T44	2		T26	3
valid_sources[0x56]	25904	1			T20	1		T23	3		T45	1
valid_sources[0x57]	24487	1			T20	2		T23	4		T22	1
valid_sources[0x58]	24510	1			T23	1		T44	1		T131	1
valid_sources[0x59]	23034	1			T23	4		T44	3		T21	1
valid_sources[0x5a]	23825	1			T23	2		T46	1		T22	3
valid_sources[0x5b]	23808	1			T23	5		T44	2		T46	3
valid_sources[0x5c]	26772	1			T23	2		T44	1		T46	1
valid_sources[0x5d]	26495	1			T131	2		T45	2		T46	1
valid_sources[0x5e]	24576	1			T19	14		T23	2		T46	4
valid_sources[0x5f]	25134	1			T20	1		T27	15		T23	3
valid_sources[0x60]	24075	1			T46	3		T22	2		T163	19
valid_sources[0x61]	23920	1			T23	1		T22	5		T126	1
valid_sources[0x62]	24630	1			T23	3		T124	2		T241	13
valid_sources[0x63]	26726	1			T23	5		T46	3		T126	1
valid_sources[0x64]	25095	1			T23	2		T46	1		T22	5
valid_sources[0x65]	23889	1			T23	1		T44	1		T22	2
valid_sources[0x66]	25240	1			T44	2		T62	2		T46	1
valid_sources[0x67]	24285	1			T20	1		T22	6		T126	8
valid_sources[0x68]	26308	1			T20	1		T23	2		T46	7
valid_sources[0x69]	24853	1			T23	2		T44	2		T22	1
valid_sources[0x6a]	26038	1			T22	1		T163	15		T126	2
valid_sources[0x6b]	26076	1			T17	3		T46	1		T22	1
valid_sources[0x6c]	23845	1			T23	2		T46	11		T22	1
valid_sources[0x6d]	25029	1			T23	3		T44	1		T131	1
valid_sources[0x6e]	23762	1			T21	1		T22	1		T204	2
valid_sources[0x6f]	25791	1			T21	1		T46	2		T22	1
valid_sources[0x70]	24808	1			T23	2		T46	7		T22	2
valid_sources[0x71]	25301	1			T23	1		T46	4		T22	1
valid_sources[0x72]	25415	1			T20	1		T23	3		T46	1
valid_sources[0x73]	22409	1			T23	1		T46	3		T204	1
valid_sources[0x74]	26630	1			T23	1		T44	1		T21	1
valid_sources[0x75]	26659	1			T23	12		T131	1		T21	1
valid_sources[0x76]	24767	1			T23	3		T26	1		T126	2
valid_sources[0x77]	26512	1			T43	2		T23	1		T131	1
valid_sources[0x78]	25218	1			T23	4		T46	1		T22	5
valid_sources[0x79]	23999	1			T43	1		T23	1		T131	1
valid_sources[0x7a]	25837	1			T23	3		T44	2		T45	1
valid_sources[0x7b]	24788	1			T23	1		T44	1		T21	1
valid_sources[0x7c]	24783	1			T23	2		T46	2		T26	8
valid_sources[0x7d]	26062	1			T43	1		T61	3		T23	2
valid_sources[0x7e]	26288	1			T23	3		T44	1		T46	1
valid_sources[0x7f]	26419	1			T23	1		T44	1		T46	1
valid_sources[0x80]	23113	1			T23	3		T126	1		T155	6

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1453735

1

T17

4

T18

7

T19

4

values[0x0]

all_enables

biggest_size

2160060

1

T17

2

T18

1

T19

3

values[0x1]

all_enables

biggest_size

2159158

1

T17

5

T18

4

T19

4