Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	100.00	1	100	1	64	64

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	0	52	100.00

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	0	52	100.00	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
non_zero_bins[0]	2816	1		T1	2	T7	5	T28	2
non_zero_bins[1]	1843	1		T1	1	T7	4	T28	1
zero	8886	1		T1	2	T2	2	T3	2

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	542	1		T28	1	T32	10	T179	1
uni	3837	1		T1	2	T28	2	T31	2
gen	4052	1		T1	1	T2	1	T3	1
res	807	1		T7	4	T8	1	T29	2
ins	4307	1		T1	2	T2	1	T3	1

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9199

mubi_true

4346

T28

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

6811

pass

6734

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	0	52	100.00
Automatically Generated Cross Bins	52	0	52	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
upd	non_zero_bins[0]	fail	mubi_false	79	1		T32	3	T179	1	T206	1
upd	non_zero_bins[0]	fail	mubi_true	67	1		T207	1	T89	1	T83	2
upd	non_zero_bins[0]	pass	mubi_false	79	1		T32	3	T82	1	T84	1
upd	non_zero_bins[0]	pass	mubi_true	53	1		T32	2	T35	1	T83	4
upd	non_zero_bins[1]	fail	mubi_false	41	1		T81	1	T84	3	T208	1
upd	non_zero_bins[1]	fail	mubi_true	50	1		T28	1	T32	1	T81	1
upd	non_zero_bins[1]	pass	mubi_false	41	1		T78	1	T83	2	T84	1
upd	non_zero_bins[1]	pass	mubi_true	36	1		T32	1	T165	1	T83	1
upd	zero	fail	mubi_false	21	1		T81	1	T82	1	T208	2
upd	zero	fail	mubi_true	32	1		T82	1	T208	1	T175	1
upd	zero	pass	mubi_false	20	1		T84	1	T208	1	T209	1
upd	zero	pass	mubi_true	23	1		T165	2	T208	2	T210	1
uni	zero	fail	mubi_false	1398	1		T1	2	T28	1	T31	2
uni	zero	fail	mubi_true	541	1		T32	8	T85	1	T81	1
uni	zero	pass	mubi_false	1355	1		T28	1	T32	17	T57	1
uni	zero	pass	mubi_true	543	1		T32	3	T34	1	T87	1
gen	non_zero_bins[0]	fail	mubi_false	270	1		T33	3	T77	3	T81	2
gen	non_zero_bins[0]	fail	mubi_true	246	1		T1	1	T28	1	T29	2
gen	non_zero_bins[0]	pass	mubi_false	256	1		T57	1	T89	1	T41	2
gen	non_zero_bins[0]	pass	mubi_true	227	1		T29	1	T32	4	T81	1
gen	non_zero_bins[1]	fail	mubi_false	166	1		T31	1	T32	2	T34	1
gen	non_zero_bins[1]	fail	mubi_true	152	1		T7	1	T32	4	T88	1
gen	non_zero_bins[1]	pass	mubi_false	153	1		T32	2	T76	1	T82	2
gen	non_zero_bins[1]	pass	mubi_true	160	1		T7	2	T32	2	T35	1
gen	zero	fail	mubi_false	992	1		T3	1	T31	1	T32	9
gen	zero	fail	mubi_true	237	1		T32	3	T56	1	T48	1
gen	zero	pass	mubi_false	983	1		T2	1	T37	1	T32	9
gen	zero	pass	mubi_true	210	1		T28	1	T38	2	T32	2
res	non_zero_bins[0]	fail	mubi_false	94	1		T29	2	T32	2	T165	1
res	non_zero_bins[0]	fail	mubi_true	95	1		T7	2	T38	1	T32	1
res	non_zero_bins[0]	pass	mubi_false	93	1		T7	1	T32	1	T82	1
res	non_zero_bins[0]	pass	mubi_true	114	1		T7	1	T38	1	T79	1
res	non_zero_bins[1]	fail	mubi_false	57	1		T31	1	T32	1	T40	1
res	non_zero_bins[1]	fail	mubi_true	71	1		T8	1	T76	1	T84	1
res	non_zero_bins[1]	pass	mubi_false	72	1		T84	1	T208	4	T175	2
res	non_zero_bins[1]	pass	mubi_true	62	1		T57	1	T82	1	T83	1
res	zero	fail	mubi_false	42	1		T41	1	T208	1	T178	1
res	zero	fail	mubi_true	29	1		T33	2	T83	1	T84	1
res	zero	pass	mubi_false	43	1		T33	2	T41	1	T83	1
res	zero	pass	mubi_true	35	1		T33	1	T175	1	T211	1
ins	non_zero_bins[0]	fail	mubi_false	286	1		T28	1	T38	1	T32	3
ins	non_zero_bins[0]	fail	mubi_true	278	1		T7	1	T33	1	T89	1
ins	non_zero_bins[0]	pass	mubi_false	293	1		T1	1	T33	1	T32	7
ins	non_zero_bins[0]	pass	mubi_true	286	1		T32	4	T79	1	T81	1
ins	non_zero_bins[1]	fail	mubi_false	194	1		T29	1	T179	1	T42	1
ins	non_zero_bins[1]	fail	mubi_true	200	1		T7	1	T32	2	T81	1
ins	non_zero_bins[1]	pass	mubi_false	160	1		T1	1	T32	5	T76	1
ins	non_zero_bins[1]	pass	mubi_true	228	1		T8	1	T32	5	T34	1
ins	zero	fail	mubi_false	1001	1		T32	13	T56	1	T105	1
ins	zero	fail	mubi_true	172	1		T31	1	T32	1	T48	1
ins	zero	pass	mubi_false	1010	1		T2	1	T3	1	T28	1
ins	zero	pass	mubi_true	199	1		T12	1	T48	1	T49	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded