Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	214957274	10501234	0	0
boot_gen_cmd_rd_A	214957274	31402	0	0
boot_ins_cmd_rd_A	214957274	35510	0	0
ctrl_rd_A	214957274	31503	0	0
err_code_test_rd_A	214957274	31640	0	0
intr_enable_rd_A	214957274	37357	0	0
max_num_reqs_between_reseeds_rd_A	214957274	36377	0	0
regwen_rd_A	214957274	35912	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	10501234	0	0
T21	1129	0	0	0
T22	7051	9	0	0
T23	10200	817	0	0
T24	1578	0	0	0
T25	954	0	0	0
T26	0	8	0	0
T44	1039	0	0	0
T45	1005	0	0	0
T46	1572	0	0	0
T62	1104	0	0	0
T124	0	825	0	0
T125	0	649	0	0
T126	0	13	0	0
T127	0	2	0	0
T128	0	10	0	0
T129	0	520	0	0
T130	0	4	0	0
T131	1076	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	31402	0	0
T21	1129	0	0	0
T22	7051	0	0	0
T23	10200	20	0	0
T24	1578	0	0	0
T25	954	0	0	0
T44	1039	0	0	0
T45	1005	0	0	0
T46	1572	0	0	0
T62	1104	0	0	0
T125	0	18	0	0
T131	1076	0	0	0
T132	0	51	0	0
T133	0	10	0	0
T134	0	3	0	0
T135	0	37	0	0
T136	0	63	0	0
T137	0	11	0	0
T138	0	21	0	0
T139	0	79	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	35510	0	0
T21	1129	0	0	0
T22	7051	0	0	0
T23	10200	12	0	0
T24	1578	0	0	0
T25	954	0	0	0
T44	1039	0	0	0
T45	1005	0	0	0
T46	1572	0	0	0
T62	1104	0	0	0
T125	0	14	0	0
T131	1076	0	0	0
T132	0	34	0	0
T133	0	4	0	0
T134	0	6	0	0
T135	0	35	0	0
T136	0	76	0	0
T137	0	7	0	0
T138	0	7	0	0
T139	0	92	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	31503	0	0
T125	10621	4	0	0
T128	7031	0	0	0
T132	2287	47	0	0
T134	1506	1	0	0
T135	0	32	0	0
T136	0	76	0	0
T137	0	17	0	0
T139	0	107	0	0
T140	0	31	0	0
T141	0	10	0	0
T142	0	4	0	0
T143	1408	0	0	0
T144	960	0	0	0
T145	1024	0	0	0
T146	1005	0	0	0
T147	855	0	0	0
T148	826	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	31640	0	0
T21	1129	0	0	0
T22	7051	0	0	0
T23	10200	12	0	0
T24	1578	0	0	0
T25	954	0	0	0
T44	1039	0	0	0
T45	1005	0	0	0
T46	1572	0	0	0
T62	1104	0	0	0
T125	0	16	0	0
T131	1076	0	0	0
T133	0	1	0	0
T134	0	9	0	0
T135	0	8	0	0
T136	0	82	0	0
T137	0	23	0	0
T138	0	26	0	0
T139	0	94	0	0
T140	0	19	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	37357	0	0
T18	1531	19	0	0
T19	1286	7	0	0
T20	1606	0	0	0
T23	10200	12	0	0
T24	0	19	0	0
T27	1235	24	0	0
T43	723	0	0	0
T44	1039	0	0	0
T45	0	5	0	0
T61	1113	0	0	0
T62	1104	0	0	0
T125	0	20	0	0
T126	0	52	0	0
T131	1076	0	0	0
T146	0	6	0	0
T149	0	22	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	36377	0	0
T19	1286	5	0	0
T20	1606	0	0	0
T23	10200	3	0	0
T27	1235	0	0	0
T43	723	0	0	0
T44	1039	0	0	0
T45	1005	8	0	0
T61	1113	0	0	0
T62	1104	0	0	0
T125	0	14	0	0
T126	0	25	0	0
T131	1076	0	0	0
T132	0	11	0	0
T133	0	5	0	0
T134	0	6	0	0
T135	0	32	0	0
T136	0	80	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	35912	0	0
T19	1286	1	0	0
T20	1606	0	0	0
T23	10200	7	0	0
T27	1235	0	0	0
T43	723	0	0	0
T44	1039	0	0	0
T45	1005	5	0	0
T61	1113	0	0	0
T62	1104	0	0	0
T125	0	14	0	0
T126	0	36	0	0
T131	1076	0	0	0
T132	0	28	0	0
T133	0	12	0	0
T134	0	5	0	0
T135	0	10	0	0
T136	0	64	0	0