Unified Coverage Report :: Module :: edn_reg_top

Module : edn_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_reg

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.07	96.30	98.49	100.00		95.54	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_alert_test_fatal_alert	100.00	100.00
u_alert_test_recov_alert	100.00	100.00
u_boot_gen_cmd	100.00	100.00	100.00			100.00
u_boot_ins_cmd	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_ctrl_auto_req_mode	100.00	100.00	100.00			100.00
u_ctrl_boot_req_mode	100.00	100.00	100.00			100.00
u_ctrl_cmd_fifo_rst	100.00	100.00	100.00			100.00
u_ctrl_edn_enable	100.00	100.00	100.00			100.00
u_err_code_edn_ack_sm_err	96.30	88.89	100.00			100.00
u_err_code_edn_cntr_err	96.30	88.89	100.00			100.00
u_err_code_edn_main_sm_err	96.30	88.89	100.00			100.00
u_err_code_fifo_read_err	96.30	88.89	100.00			100.00
u_err_code_fifo_state_err	96.30	88.89	100.00			100.00
u_err_code_fifo_write_err	96.30	88.89	100.00			100.00
u_err_code_sfifo_gencmd_err	96.30	88.89	100.00			100.00
u_err_code_sfifo_rescmd_err	96.30	88.89	100.00			100.00
u_err_code_test	100.00	100.00	100.00			100.00
u_err_code_test0_qe	100.00	100.00				100.00
u_generate_cmd	100.00	100.00
u_intr_enable_edn_cmd_req_done	100.00	100.00	100.00			100.00
u_intr_enable_edn_fatal_err	100.00	100.00	100.00			100.00
u_intr_state_edn_cmd_req_done	100.00	100.00	100.00			100.00
u_intr_state_edn_fatal_err	100.00	100.00	100.00			100.00
u_intr_test_edn_cmd_req_done	100.00	100.00
u_intr_test_edn_fatal_err	100.00	100.00
u_main_sm_state	62.59	77.78	50.00			60.00
u_max_num_reqs_between_reseeds	100.00	100.00	100.00			100.00
u_max_num_reqs_between_reseeds0_qe	100.00	100.00				100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_recov_alert_sts_auto_req_mode_field_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_boot_req_mode_field_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_cmd_fifo_rst_field_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_edn_bus_cmp_alert	100.00	100.00	100.00			100.00
u_recov_alert_sts_edn_enable_field_alert	100.00	100.00	100.00			100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_regwen	100.00	100.00	100.00			100.00
u_reseed_cmd	100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_sw_cmd_req	100.00	100.00
u_sw_cmd_sts_cmd_ack	62.59	77.78	50.00			60.00
u_sw_cmd_sts_cmd_rdy	62.59	77.78	50.00			60.00
u_sw_cmd_sts_cmd_reg_rdy	62.59	77.78	50.00			60.00
u_sw_cmd_sts_cmd_sts	62.59	77.78	50.00			60.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_reg_top

	Line No.	Total	Covered	Percent
TOTAL		143	143	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	311	1	1	100.00
CONT_ASSIGN	326	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	363	1	1	100.00
CONT_ASSIGN	379	1	1	100.00
CONT_ASSIGN	413	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
CONT_ASSIGN	596	1	1	100.00
CONT_ASSIGN	712	1	1	100.00
CONT_ASSIGN	726	1	1	100.00
CONT_ASSIGN	732	1	1	100.00
CONT_ASSIGN	746	1	1	100.00
CONT_ASSIGN	786	1	1	100.00
CONT_ASSIGN	1181	1	1	100.00
ALWAYS	1215	18	18	100.00
CONT_ASSIGN	1235	1	1	100.00
ALWAYS	1239	1	1	100.00
CONT_ASSIGN	1260	1	1	100.00
CONT_ASSIGN	1262	1	1	100.00
CONT_ASSIGN	1264	1	1	100.00
CONT_ASSIGN	1265	1	1	100.00
CONT_ASSIGN	1267	1	1	100.00
CONT_ASSIGN	1269	1	1	100.00
CONT_ASSIGN	1270	1	1	100.00
CONT_ASSIGN	1272	1	1	100.00
CONT_ASSIGN	1274	1	1	100.00
CONT_ASSIGN	1275	1	1	100.00
CONT_ASSIGN	1277	1	1	100.00
CONT_ASSIGN	1279	1	1	100.00
CONT_ASSIGN	1280	1	1	100.00
CONT_ASSIGN	1282	1	1	100.00
CONT_ASSIGN	1283	1	1	100.00
CONT_ASSIGN	1285	1	1	100.00
CONT_ASSIGN	1287	1	1	100.00
CONT_ASSIGN	1289	1	1	100.00
CONT_ASSIGN	1291	1	1	100.00
CONT_ASSIGN	1292	1	1	100.00
CONT_ASSIGN	1294	1	1	100.00
CONT_ASSIGN	1295	1	1	100.00
CONT_ASSIGN	1297	1	1	100.00
CONT_ASSIGN	1298	1	1	100.00
CONT_ASSIGN	1300	1	1	100.00
CONT_ASSIGN	1301	1	1	100.00
CONT_ASSIGN	1303	1	1	100.00
CONT_ASSIGN	1304	1	1	100.00
CONT_ASSIGN	1306	1	1	100.00
CONT_ASSIGN	1307	1	1	100.00
CONT_ASSIGN	1309	1	1	100.00
CONT_ASSIGN	1310	1	1	100.00
CONT_ASSIGN	1312	1	1	100.00
CONT_ASSIGN	1314	1	1	100.00
CONT_ASSIGN	1316	1	1	100.00
CONT_ASSIGN	1318	1	1	100.00
CONT_ASSIGN	1320	1	1	100.00
CONT_ASSIGN	1321	1	1	100.00
CONT_ASSIGN	1323	1	1	100.00
ALWAYS	1327	18	18	100.00
ALWAYS	1349	40	40	100.00
CONT_ASSIGN	1451	0	0
CONT_ASSIGN	1459	1	1	100.00
CONT_ASSIGN	1460	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
68	1	1
69	1	1
70	1	1
71	1	1
			MISSING_ELSE
77	1	1
89	1	1
90	1	1
118	1	1
119	1	1
311	1	1
326	1	1
342	1	1
348	1	1
363	1	1
379	1	1
413	1	1
582	1	1
596	1	1
712	1	1
726	1	1
732	1	1
746	1	1
786	1	1
1181	1	1
1215	1	1
1216	1	1
1217	1	1
1218	1	1
1219	1	1
1220	1	1
1221	1	1
1222	1	1
1223	1	1
1224	1	1
1225	1	1
1226	1	1
1227	1	1
1228	1	1
1229	1	1
1230	1	1
1231	1	1
1232	1	1
1235	1	1
1239	1	1
1260	1	1
1262	1	1
1264	1	1
1265	1	1
1267	1	1
1269	1	1
1270	1	1
1272	1	1
1274	1	1
1275	1	1
1277	1	1
1279	1	1
1280	1	1
1282	1	1
1283	1	1
1285	1	1
1287	1	1
1289	1	1
1291	1	1
1292	1	1
1294	1	1
1295	1	1
1297	1	1
1298	1	1
1300	1	1
1301	1	1
1303	1	1
1304	1	1
1306	1	1
1307	1	1
1309	1	1
1310	1	1
1312	1	1
1314	1	1
1316	1	1
1318	1	1
1320	1	1
1321	1	1
1323	1	1
1327	1	1
1328	1	1
1329	1	1
1330	1	1
1331	1	1
1332	1	1
1333	1	1
1334	1	1
1335	1	1
1336	1	1
1337	1	1
1338	1	1
1339	1	1
1340	1	1
1341	1	1
1342	1	1
1343	1	1
1344	1	1
1349	1	1
1350	1	1
1352	1	1
1353	1	1
1357	1	1
1358	1	1
1362	1	1
1363	1	1
1367	1	1
1368	1	1
1372	1	1
1376	1	1
1377	1	1
1378	1	1
1379	1	1
1383	1	1
1387	1	1
1391	1	1
1395	1	1
1396	1	1
1397	1	1
1398	1	1
1402	1	1
1406	1	1
1410	1	1
1414	1	1
1415	1	1
1416	1	1
1417	1	1
1418	1	1
1422	1	1
1423	1	1
1424	1	1
1425	1	1
1426	1	1
1427	1	1
1428	1	1
1429	1	1
1433	1	1
1437	1	1
1451		unreachable
1459	1	1
1460	1	1

---

Cond Coverage for Module : edn_reg_top

	Total	Covered	Percent
Conditions	184	184	100.00
Logical	184	184	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T23,T22,T126
1	1	Covered	T17,T18,T19

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T4,T15,T16
1	0	Covered	T22,T26,T126

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T17,T18,T19
0	0	1	Covered	T4,T15,T16
0	1	0	Covered	T22,T26,T126
1	0	0	Covered	T22,T26,T126

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T17,T18,T19
0	0	1	Covered	T22,T26,T126
0	1	0	Covered	T23,T124,T125
1	0	0	Covered	T23,T124,T125

 LINE       413
 EXPRESSION (ctrl_we & regwen_qs)
             ---1---   ----2----

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T166,T167,T168
1	1	Covered	T1,T2,T3

 LINE       1216
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_STATE_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       1217
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_ENABLE_OFFSET)
            ------------------------1------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       1218
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_INTR_TEST_OFFSET)
            -----------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T18,T20,T27

 LINE       1219
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ALERT_TEST_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T19,T20

 LINE       1220
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_REGWEN_OFFSET)
            ----------------------1---------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T19,T20

 LINE       1221
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_CTRL_OFFSET)
            ---------------------1--------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T20,T23,T44

 LINE       1222
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_BOOT_INS_CMD_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T20,T23,T44

 LINE       1223
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_BOOT_GEN_CMD_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T20,T23,T44

 LINE       1224
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_SW_CMD_REQ_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T19,T20

 LINE       1225
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_SW_CMD_STS_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T19,T20

 LINE       1226
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_RESEED_CMD_OFFSET)
            ------------------------1-----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T19,T20

 LINE       1227
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_GENERATE_CMD_OFFSET)
            -------------------------1------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T19,T20

 LINE       1228
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_MAX_NUM_REQS_BETWEEN_RESEEDS_OFFSET)
            ---------------------------------1--------------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T19,T20

 LINE       1229
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_RECOV_ALERT_STS_OFFSET)
            --------------------------1--------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T19,T20

 LINE       1230
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ERR_CODE_OFFSET)
            -----------------------1----------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T19,T20

 LINE       1231
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_ERR_CODE_TEST_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T20,T23,T44

 LINE       1232
 EXPRESSION (reg_addr == edn_reg_pkg::EDN_MAIN_SM_STATE_OFFSET)
            -------------------------1-------------------------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T19,T20

 LINE       1235
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T17,T18,T19
1	Covered	T17,T18,T19

 LINE       1235
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T17,T18,T19
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19

 LINE       1239
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19
1	1	Covered	T23,T22,T26

 LINE       1239
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b1 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b1 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0011 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b1111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b1111 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0011 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b1111 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b1 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0011 & (~reg_be))))))

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	-17-	Status	Tests
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T17,T18,T19
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	Covered	T19,T20,T23
0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	Covered	T23,T21,T24
0	0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	Covered	T17,T19,T20
0	0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	Covered	T23,T22,T163
0	0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	Covered	T19,T23,T22
0	0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	Covered	T17,T43,T23
0	0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	Covered	T17,T20,T23
0	0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	Covered	T20,T23,T21
0	0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	Covered	T23,T45,T21
0	0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	Covered	T20,T23,T21
0	0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	Covered	T20,T23,T24
0	0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	Covered	T20,T23,T21
0	0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T23,T45,T21
0	0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T17,T20,T23
0	0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T18,T20,T27
0	1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T18,T27,T61
1	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	0	Covered	T18,T19,T27

 LINE       1239
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T20
1	1	Covered	T18,T19,T27

 LINE       1239
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T18,T19
1	1	Covered	T18,T27,T61

 LINE       1239
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T18,T20,T27
1	1	Covered	T18,T20,T27

 LINE       1239
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T20
1	1	Covered	T17,T20,T23

 LINE       1239
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T20
1	1	Covered	T23,T45,T21

 LINE       1239
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T23,T44,T21
1	1	Covered	T20,T23,T21

 LINE       1239
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T20,T23,T44
1	1	Covered	T20,T23,T24

 LINE       1239
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T23,T44,T46
1	1	Covered	T20,T23,T21

 LINE       1239
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T20
1	1	Covered	T23,T45,T21

 LINE       1239
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T20
1	1	Covered	T20,T23,T21

 LINE       1239
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T20
1	1	Covered	T17,T20,T23

 LINE       1239
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T20
1	1	Covered	T17,T43,T23

 LINE       1239
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T20
1	1	Covered	T19,T23,T22

 LINE       1239
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T20
1	1	Covered	T23,T22,T163

 LINE       1239
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T20
1	1	Covered	T17,T19,T20

 LINE       1239
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T20,T23,T44
1	1	Covered	T23,T21,T24

 LINE       1239
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T17,T18,T19
1	0	Covered	T17,T19,T20
1	1	Covered	T19,T20,T23

 LINE       1260
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T17,T18,T19
1	1	0	Covered	T23,T22,T26
1	1	1	Covered	T18,T27,T61

 LINE       1265
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T17,T18,T19
1	1	0	Covered	T23,T124,T125
1	1	1	Covered	T17,T18,T19

 LINE       1270
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T18,T20,T27
1	1	0	Covered	T23,T26,T124
1	1	1	Covered	T18,T20,T27

 LINE       1275
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T17,T19,T20
1	1	0	Covered	T124,T125,T129
1	1	1	Covered	T17,T19,T20

 LINE       1280
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T17,T19,T20
1	1	0	Covered	T23,T124,T129
1	1	1	Covered	T17,T19,T20

 LINE       1283
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T20,T23,T44
1	1	0	Covered	T126,T125,T129
1	1	1	Covered	T1,T2,T3

 LINE       1292
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T20,T23,T44
1	1	0	Covered	T124,T125,T128
1	1	1	Covered	T28,T37,T31

 LINE       1295
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T20,T23,T44
1	1	0	Covered	T23,T125,T151
1	1	1	Covered	T28,T37,T31

 LINE       1298
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T17,T19,T20
1	1	0	Covered	T23,T125,T151
1	1	1	Covered	T17,T19,T20

 LINE       1301
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T17,T19,T20
1	1	0	Covered	T23,T124,T125
1	1	1	Covered	T17,T19,T20

 LINE       1304
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T17,T19,T20
1	1	0	Covered	T23,T124,T125
1	1	1	Covered	T17,T19,T20

 LINE       1307
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T17,T19,T20
1	1	0	Covered	T23,T124,T129
1	1	1	Covered	T17,T19,T20

 LINE       1310
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T17,T19,T20
1	1	0	Covered	T23,T22,T124
1	1	1	Covered	T17,T19,T20

 LINE       1321
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T17,T18,T19
1	0	1	Covered	T20,T23,T44
1	1	0	Covered	T124,T127,T151
1	1	1	Covered	T1,T2,T3

---

Branch Coverage for Module : edn_reg_top

	Line No.	Total	Covered	Percent
Branches		23	23	100.00
TERNARY	1235	2	2	100.00
IF	68	3	3	100.00
CASE	1350	18	18	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	1235	((reg_re || reg_we)) ? 

Branches:

-1-	Status	Tests
1	Covered	T17,T18,T19
0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	68	if ((!rst_ni))
-2-:	70	if ((intg_err || reg_we_err))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T17,T18,T19
0	1	Covered	T22,T26,T126
0	0	Covered	T17,T18,T19

	LineNo.	Expression
-1-:	1350	case (1'b1)

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T17,T18,T19
addr_hit[1]	Covered	T17,T18,T19
addr_hit[2]	Covered	T17,T18,T19
addr_hit[3]	Covered	T17,T18,T19
addr_hit[4]	Covered	T17,T18,T19
addr_hit[5]	Covered	T17,T18,T19
addr_hit[6]	Covered	T17,T18,T19
addr_hit[7]	Covered	T17,T18,T19
addr_hit[8]	Covered	T17,T18,T19
addr_hit[9]	Covered	T17,T18,T19
addr_hit[10]	Covered	T17,T18,T19
addr_hit[11]	Covered	T17,T18,T19
addr_hit[12]	Covered	T17,T18,T19
addr_hit[13]	Covered	T17,T18,T19
addr_hit[14]	Covered	T17,T18,T19
addr_hit[15]	Covered	T17,T18,T19
addr_hit[16]	Covered	T17,T18,T19
default	Covered	T17,T18,T19

---

Assert Coverage for Module : edn_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	214957274	780453	0	0
reAfterRv	214957274	780451	0	0
rePulse	214957274	309704	0	0
wePulse	214957274	470747	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	780453	0	0
T17	1459	21	0	0
T18	1531	40	0	0
T19	1286	28	0	0
T20	1606	54	0	0
T23	10200	31	0	0
T27	1235	38	0	0
T43	723	26	0	0
T44	1039	137	0	0
T61	1113	40	0	0
T62	1104	20	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	780451	0	0
T17	1459	21	0	0
T18	1531	40	0	0
T19	1286	28	0	0
T20	1606	54	0	0
T23	10200	31	0	0
T27	1235	38	0	0
T43	723	26	0	0
T44	1039	137	0	0
T61	1113	40	0	0
T62	1104	20	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	309704	0	0
T17	1459	10	0	0
T18	1531	20	0	0
T19	1286	17	0	0
T20	1606	30	0	0
T23	10200	6	0	0
T27	1235	19	0	0
T43	723	16	0	0
T44	1039	84	0	0
T61	1113	20	0	0
T62	1104	10	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	214957274	470747	0	0
T17	1459	11	0	0
T18	1531	20	0	0
T19	1286	11	0	0
T20	1606	24	0	0
T23	10200	25	0	0
T27	1235	19	0	0
T43	723	10	0	0
T44	1039	53	0	0
T61	1113	20	0	0
T62	1104	10	0	0