Unified Coverage Report :: Cond split page

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 LINE       270
 EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
             ------------1------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T28
1	1	Covered	T1,T2,T3

 LINE       275
 EXPRESSION (edn_cntr_err_sum || edn_main_sm_err_sum || edn_ack_sm_err_sum)
             --------1-------    ---------2---------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T4,T58,T63
0	1	0	Covered	T4,T6,T64
1	0	0	Covered	T2,T3,T4

 LINE       280
 EXPRESSION ((edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)) || fatal_loc_events)
             -------------------------------------1-------------------------------------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T59,T60,T65

 LINE       280
 SUB-EXPRESSION (edn_enable_fo[FatalErr] && (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum))
                 -----------1-----------    -----------------------2----------------------

-1-	-2-	Status	Tests
0	1	Covered	T59,T60,T65
1	0	Covered	T1,T2,T3
1	1	Covered	T59,T60,T65

 LINE       280
 SUB-EXPRESSION (sfifo_rescmd_err_sum || sfifo_gencmd_err_sum)
                 ----------1---------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T60,T66,T67
1	0	Covered	T59,T65,T68

 LINE       286
 EXPRESSION (((|sfifo_rescmd_err)) || err_code_test_bit[0])
             ----------1----------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T59,T65,T68

 LINE       288
 EXPRESSION (((|sfifo_gencmd_err)) || err_code_test_bit[1])
             ----------1----------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T60,T66,T67

 LINE       290
 EXPRESSION (((|edn_ack_sm_err)) || err_code_test_bit[20])
             ---------1---------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       292
 EXPRESSION (edn_main_sm_err || err_code_test_bit[21])
             -------1-------    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       294
 EXPRESSION (edn_cntr_err || err_code_test_bit[22])
             ------1-----    ----------2----------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T2,T3,T4

 LINE       297
 EXPRESSION (sfifo_rescmd_err[2] || sfifo_gencmd_err[2] || err_code_test_bit[28])
             ---------1---------    ---------2---------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T69,T70
1	0	0	Covered	T68,T71,T72

 LINE       301
 EXPRESSION (sfifo_rescmd_err[1] || sfifo_gencmd_err[1] || err_code_test_bit[29])
             ---------1---------    ---------2---------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T60,T66,T67
1	0	0	Covered	T59,T73,T74

 LINE       305
 EXPRESSION (sfifo_rescmd_err[0] || sfifo_gencmd_err[0] || err_code_test_bit[30])
             ---------1---------    ---------2---------    ----------3----------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Not Covered
0	1	0	Covered	T75,T69,T70
1	0	0	Covered	T65,T68,T71

 LINE       313
 EXPRESSION (edn_enable_fo[ReseedCmdErr] && sfifo_rescmd_err_sum)
             -------------1-------------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T59,T65,T68
1	0	Covered	T1,T2,T3
1	1	Covered	T59,T65,T68

 LINE       316
 EXPRESSION (edn_enable_fo[GenCmdErr] && sfifo_gencmd_err_sum)
             ------------1-----------    ----------2---------

-1-	-2-	Status	Tests
0	1	Covered	T60,T66,T67
1	0	Covered	T1,T2,T3
1	1	Covered	T60,T66,T67

 LINE       333
 EXPRESSION (edn_enable_fo[FifoWrErr] && fifo_write_err_sum)
             ------------1-----------    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T68,T71,T69
1	0	Covered	T1,T2,T3
1	1	Covered	T68,T71,T69

 LINE       336
 EXPRESSION (edn_enable_fo[FifoRdErr] && fifo_read_err_sum)
             ------------1-----------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T59,T60,T66
1	0	Covered	T1,T2,T3
1	1	Covered	T59,T60,T66

 LINE       339
 EXPRESSION (edn_enable_fo[FifoStErr] && fifo_status_err_sum)
             ------------1-----------    ---------2---------

-1-	-2-	Status	Tests
0	1	Covered	T65,T68,T75
1	0	Covered	T1,T2,T3
1	1	Covered	T65,T68,T75

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 0) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Not Covered

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 0)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 1) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 1)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 2) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 2)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 3) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T28,T50,T59
1	1	Covered	T28,T50,T59

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 3)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T50,T59

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 4) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T31,T76
1	1	Covered	T8,T31,T76

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 4)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T31,T76

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 5) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T33,T32
1	1	Covered	T2,T33,T32

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 5)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T33,T32

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 6) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T57,T77
1	1	Covered	T32,T57,T77

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 6)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T57,T77

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 7) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T78,T79,T80
1	1	Covered	T78,T79,T80

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 7)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T78,T79,T80

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 8) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T81,T82
1	1	Covered	T32,T81,T82

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 8)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T81,T82

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 9) && reg2hw.err_code_test.qe)
             --------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T32,T82
1	1	Covered	T3,T32,T82

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 9)
                --------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T32,T82

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 10) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T34,T83,T84
1	1	Covered	T34,T83,T84

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 10)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T34,T83,T84

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 11) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T32,T85
1	1	Covered	T29,T32,T85

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 11)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T29,T32,T85

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 12) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T12,T82
1	1	Covered	T32,T12,T82

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 12)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T12,T82

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 13) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T83,T52,T84
1	1	Covered	T83,T52,T84

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 13)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T83,T52,T84

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 14) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T86,T83
1	1	Covered	T32,T86,T83

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 14)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T86,T83

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 15) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T3,T33,T38
1	1	Covered	T3,T33,T38

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 15)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T3,T33,T38

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 16) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T81,T83,T63
1	1	Covered	T81,T83,T63

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 16)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T81,T83,T63

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 17) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T82,T13
1	1	Covered	T32,T82,T13

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 17)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T82,T13

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 18) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T8,T87,T82
1	1	Covered	T8,T87,T82

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 18)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T8,T87,T82

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 19) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T88,T89,T81
1	1	Covered	T88,T89,T81

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 19)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T88,T89,T81

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 20) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 20)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 21) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 21)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 22) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 22)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 23) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T37,T32
1	1	Covered	T2,T37,T32

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 23)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T37,T32

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 24) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T28
1	0	Covered	T1,T32,T41
1	1	Covered	T1,T32,T41

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 24)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T32,T41

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 25) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T81,T82
1	1	Covered	T32,T81,T82

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 25)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T81,T82

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 26) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T50,T82
1	1	Covered	T32,T50,T82

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 26)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T50,T82

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 27) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T32,T81,T82
1	1	Covered	T32,T81,T82

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 27)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T32,T81,T82

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 28) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 28)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 29) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 29)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       344
 EXPRESSION ((reg2hw.err_code_test.q == 30) && reg2hw.err_code_test.qe)
             ---------------1--------------    -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Not Covered

 LINE       344
 SUB-EXPRESSION (reg2hw.err_code_test.q == 30)
                ---------------1--------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Not Covered

 LINE       349
 EXPRESSION (edn_bus_cmp_alert || cmd_fifo_rst_pfa || auto_req_mode_pfa || boot_req_mode_pfa || edn_enable_pfa)
             --------1--------    --------2-------    --------3--------    --------4--------    -------5------

-1-	-2-	-3-	-4-	-5-	Status	Tests
0	0	0	0	0	Covered	T1,T2,T3
0	0	0	0	1	Covered	T12,T13,T14
0	0	0	1	0	Covered	T90,T91,T92
0	0	1	0	0	Covered	T93,T94,T95
0	1	0	0	0	Covered	T96,T97,T98
1	0	0	0	0	Covered	T12,T13,T14

 LINE       371
 SUB-EXPRESSION (reg2hw.alert_test.recov_alert.q && reg2hw.alert_test.recov_alert.qe)
                 ---------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T47,T99,T100
1	0	Covered	T1,T2,T3
1	1	Covered	T47,T99,T100

 LINE       375
 SUB-EXPRESSION (reg2hw.alert_test.fatal_alert.q && reg2hw.alert_test.fatal_alert.qe)
                 ---------------1---------------    ----------------2---------------

-1-	-2-	Status	Tests
0	1	Covered	T47,T99,T100
1	0	Covered	T1,T2,T3
1	1	Covered	T47,T99,T100

 LINE       451
 EXPRESSION (reg2hw.sw_cmd_req.qe && cmd_reg_rdy_q)
             ----------1---------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T29,T38,T41
1	1	Covered	T1,T2,T3

 LINE       463
 EXPRESSION (cs_cmd_req_vld_out_q && send_cs_cmd_gated)
             ----------1---------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       464
 EXPRESSION (cs_cmd_req_vld_out_q && send_gencmd_gated)
             ----------1---------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T7,T8

 LINE       465
 EXPRESSION (cs_cmd_req_vld_out_q && send_rescmd_gated)
             ----------1---------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T7,T8,T29

 LINE       468
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReq])) ? '0 : (boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       468
 SUB-EXPRESSION 
 Number  Term
      1  boot_wr_ins_cmd ? boot_ins_cmd : (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T37,T31

 LINE       468
 SUB-EXPRESSION (boot_wr_gen_cmd ? boot_gen_cmd : (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T37,T31

 LINE       468
 SUB-EXPRESSION (boot_wr_uni_cmd ? 32'b00000000000000000000000000000101 : (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T28,T31,T78

 LINE       468
 SUB-EXPRESSION (sw_cmd_req_load ? sw_cmd_req_bus : cs_cmd_req_q)
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       477
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValid])) ? '0 : (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       477
 SUB-EXPRESSION (cs_cmd_handshake ? '0 : ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q))
                 --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       477
 SUB-EXPRESSION ((sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd) ? 1'b1 : cs_cmd_req_vld_q)
                 -------------------------------------1------------------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       477
 SUB-EXPRESSION (sw_cmd_req_load || boot_wr_ins_cmd || boot_wr_gen_cmd || boot_wr_uni_cmd)
                 -------1-------    -------2-------    -------3-------    -------4-------

-1-	-2-	-3-	-4-	Status	Tests
0	0	0	0	Covered	T1,T2,T3
0	0	0	1	Covered	T28,T31,T78
0	0	1	0	Covered	T28,T37,T31
0	1	0	0	Covered	T28,T37,T31
1	0	0	0	Covered	T1,T2,T3

 LINE       484
 EXPRESSION (cs_cmd_req_vld_q && csrng_cmd_i.csrng_req_ready)
             --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       488
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqOut])) ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       488
 SUB-EXPRESSION 
 Number  Term
      1  (send_rescmd || capt_rescmd_fifo_cnt) ? (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q) : ((send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T29

 LINE       488
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T29
1	0	Covered	T7,T8,T29

 LINE       488
 SUB-EXPRESSION (sfifo_rescmd_pop ? sfifo_rescmd_rdata : cs_cmd_req_out_q)
                 --------1-------

-1-	Status	Tests
0	Covered	T7,T8,T29
1	Covered	T7,T8,T29

 LINE       488
 SUB-EXPRESSION 
 Number  Term
      1  (send_gencmd || capt_gencmd_fifo_cnt) ? (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q) : ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       488
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T7,T8

 LINE       488
 SUB-EXPRESSION (sfifo_gencmd_pop ? sfifo_gencmd_rdata : cs_cmd_req_out_q)
                 --------1-------

-1-	Status	Tests
0	Covered	T2,T7,T8
1	Covered	T2,T7,T8

 LINE       488
 SUB-EXPRESSION ((cs_cmd_req_vld_q && ((!cs_cmd_handshake))) ? cs_cmd_req_q : cs_cmd_req_out_q)
                 ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       488
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       504
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CsrngCmdReqValidOut])) ? '0 : (cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       504
 SUB-EXPRESSION 
 Number  Term
      1  cmd_sent ? '0 : ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       504
 SUB-EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt) ? 1'b1 : ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))))
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T29

 LINE       504
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T29
1	0	Covered	T7,T8,T29

 LINE       504
 SUB-EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) ? 1'b1 : (cs_cmd_req_vld_q && ((!cs_cmd_handshake))))
                 ------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       504
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T7,T8

 LINE       504
 SUB-EXPRESSION (cs_cmd_req_vld_q && ((!cs_cmd_handshake)))
                 --------1-------    ----------2----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       519
 EXPRESSION (((!sw_cmd_req_load)) && cmd_rdy_d && cmd_reg_rdy_d)
             ----------1---------    ----2----    ------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       523
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       523
 SUB-EXPRESSION (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))))
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       523
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       523
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       523
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack ? 1'b1 : cmd_rdy_q)
                 ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       534
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       534
 SUB-EXPRESSION (((!sw_cmd_valid)) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))))
                 --------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T3,T7

 LINE       534
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       534
 SUB-EXPRESSION (accept_sw_cmds_pulse ? 1'b1 : (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       534
 SUB-EXPRESSION (cs_cmd_handshake ? 1'b1 : cmd_reg_rdy_q)
                 --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       545
 EXPRESSION (((!edn_enable_fo[SwCmdSts])) ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q))
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       545
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? csrng_cmd_i.csrng_rsp_sts : csrng_cmd_sts_q)
                 ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       545
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
                 ------------1------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T28
1	1	Covered	T1,T2,T3

 LINE       553
 EXPRESSION (((!edn_enable_fo[SwCmdSts])) ? 1'b0 : (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_cmd_ack_q)))
             --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       553
 SUB-EXPRESSION (sw_cmd_req_load ? 1'b0 : ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_cmd_ack_q))
                 -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       553
 SUB-EXPRESSION ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid) ? 1'b1 : csrng_cmd_ack_q)
                 ---------------------1---------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       553
 SUB-EXPRESSION (csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)
                 ------------1------------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T28
1	1	Covered	T1,T2,T3

 LINE       580
 EXPRESSION ((send_rescmd || capt_rescmd_fifo_cnt) && csrng_cmd_i.csrng_req_ready)
             ------------------1------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T29
1	1	Covered	T7,T8,T29

 LINE       580
 SUB-EXPRESSION (send_rescmd || capt_rescmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T29
1	0	Covered	T7,T8,T29

 LINE       582
 EXPRESSION (rescmd_handshake ? 1'b1 : reseed_cmd_load)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T29

 LINE       586
 EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : reseed_cmd_bus)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       590
 EXPRESSION ((rescmd_handshake && ((!cmd_sent))) || capt_rescmd_fifo_cnt)
             -----------------1-----------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T29
1	0	Covered	T7,T8,T29

 LINE       590
 SUB-EXPRESSION (rescmd_handshake && ((!cmd_sent)))
                 --------1-------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T29
1	1	Covered	T7,T8,T29

 LINE       592
 EXPRESSION (cmd_fifo_rst_fo[1] || main_sm_done_pulse)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7

 LINE       594
 SUB-EXPRESSION (sfifo_rescmd_push && sfifo_rescmd_full)
                 --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T40,T65,T101
1	0	Covered	T2,T7,T8
1	1	Covered	T68,T71,T72

 LINE       594
 SUB-EXPRESSION (sfifo_rescmd_pop && ((!sfifo_rescmd_not_empty)))
                 --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T7,T8,T29
1	1	Covered	T59,T73,T74

 LINE       594
 SUB-EXPRESSION (sfifo_rescmd_full && ((!sfifo_rescmd_not_empty)))
                 --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T40,T68,T101
1	1	Covered	T65,T68,T71

 LINE       620
 EXPRESSION ((send_gencmd || capt_gencmd_fifo_cnt) && csrng_cmd_i.csrng_req_ready)
             ------------------1------------------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T7,T8

 LINE       620
 SUB-EXPRESSION (send_gencmd || capt_gencmd_fifo_cnt)
                 -----1-----    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T7,T8

 LINE       622
 EXPRESSION (gencmd_handshake ? 1'b1 : generate_cmd_load)
             --------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       626
 EXPRESSION (auto_req_mode_busy ? cs_cmd_req_out_q : generate_cmd_bus)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       630
 EXPRESSION ((gencmd_handshake && ((!cmd_sent))) || capt_gencmd_fifo_cnt)
             -----------------1-----------------    ----------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T7,T8
1	0	Covered	T7,T8,T29

 LINE       630
 SUB-EXPRESSION (gencmd_handshake && ((!cmd_sent)))
                 --------1-------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T7,T8,T29

 LINE       632
 EXPRESSION (cmd_fifo_rst_fo[2] || main_sm_done_pulse)
             ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T7

 LINE       634
 SUB-EXPRESSION (sfifo_gencmd_push && sfifo_gencmd_full)
                 --------1--------    --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T2,T7,T8
1	1	Covered	T69,T70

 LINE       634
 SUB-EXPRESSION (sfifo_gencmd_pop && ((!sfifo_gencmd_not_empty)))
                 --------1-------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T60,T66,T67

 LINE       634
 SUB-EXPRESSION (sfifo_gencmd_full && ((!sfifo_gencmd_not_empty)))
                 --------1--------    -------------2-------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T7,T8
1	1	Covered	T75,T69,T70

 LINE       675
 EXPRESSION (send_gencmd && cmd_sent)
             -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T29
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T7,T8

 LINE       691
 EXPRESSION (max_reqs_between_reseed_load || (send_rescmd && cmd_sent) || main_sm_done_pulse)
             --------------1-------------    ------------2------------    ---------3--------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	1	0	Covered	T7,T8,T29
1	0	0	Covered	T2,T7,T8

 LINE       691
 SUB-EXPRESSION (send_rescmd && cmd_sent)
                 -----1-----    ----2---

-1-	-2-	Status	Tests
0	1	Covered	T2,T7,T8
1	0	Covered	T7,T8,T29
1	1	Covered	T7,T8,T29

 LINE       695
 EXPRESSION (max_reqs_cnt == '0)
            ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       698
 EXPRESSION 
 Number  Term
      1  ((!edn_enable_fo[CmdFifoCnt])) ? '0 : ((cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 : (capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       698
 SUB-EXPRESSION 
 Number  Term
      1  (cmd_fifo_rst_fo[3] || main_sm_done_pulse) ? '0 : (capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T3,T28

 LINE       698
 SUB-EXPRESSION (cmd_fifo_rst_fo[3] || main_sm_done_pulse)
                 ---------1--------    ---------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T28
1	0	Covered	T12,T13,T14

 LINE       698
 SUB-EXPRESSION 
 Number  Term
      1  capt_gencmd_fifo_cnt ? sfifo_gencmd_depth : (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)))

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       698
 SUB-EXPRESSION (capt_rescmd_fifo_cnt ? sfifo_rescmd_depth : ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q))
                 ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T29

 LINE       698
 SUB-EXPRESSION ((sfifo_gencmd_pop || sfifo_rescmd_pop) ? ((cmd_fifo_cnt_q - 1)) : cmd_fifo_cnt_q)
                 -------------------1------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T7,T8,T29

 LINE       698
 SUB-EXPRESSION (sfifo_gencmd_pop || sfifo_rescmd_pop)
                 --------1-------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T29
1	0	Covered	T7,T8,T29

 LINE       708
 EXPRESSION ((cmd_fifo_cnt_q == 4'(1)) && (gencmd_handshake || rescmd_handshake))
             ------------1------------    -------------------2------------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T29
1	0	Covered	T2,T7,T8
1	1	Covered	T2,T7,T8

 LINE       708
 SUB-EXPRESSION (cmd_fifo_cnt_q == 4'(1))
                ------------1------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T7,T8

 LINE       708
 SUB-EXPRESSION (gencmd_handshake || rescmd_handshake)
                 --------1-------    --------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T29
1	0	Covered	T2,T7,T8

 LINE       755
 EXPRESSION (((!packer_ep_rvalid[0])) && edn_i[0].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T31
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T4

 LINE       755
 EXPRESSION (((!packer_ep_rvalid[1])) && edn_i[1].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T28,T8

 LINE       755
 EXPRESSION (((!packer_ep_rvalid[2])) && edn_i[2].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T7,T29

 LINE       755
 EXPRESSION (((!packer_ep_rvalid[3])) && edn_i[3].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T29
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T29

 LINE       755
 EXPRESSION (((!packer_ep_rvalid[4])) && edn_i[4].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T28,T8
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T28,T8

 LINE       755
 EXPRESSION (((!packer_ep_rvalid[5])) && edn_i[5].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T29,T30
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T29,T30

 LINE       755
 EXPRESSION (((!packer_ep_rvalid[6])) && edn_i[6].edn_req)
             ------------1-----------    --------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T28
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T28

 LINE       786
 EXPRESSION (((!edn_enable_fo[CsrngFipsEn])) ? 1'b0 : ((packer_cs_push && packer_cs_wready) ? csrng_cmd_i.genbits_fips : csrng_fips_q))
             ---------------1---------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3