Unified Coverage Report :: Module :: edn_core

Module : edn_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.57	100.00	89.71			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core	96.57	100.00	89.71			100.00

---

Module Instance : tb.dut.u_edn_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.57	100.00	89.71			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
82.93	99.92	92.02	17.82	89.47	99.52	98.85

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ep_blk[0].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[0].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[1].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[2].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[3].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[4].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[5].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
gen_ep_blk[6].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
u_edn_main_sm	98.15	100.00	100.00		90.74	100.00	100.00
u_intr_hw_edn_cmd_req_done	100.00	100.00	100.00			100.00	100.00
u_intr_hw_edn_fatal_err	100.00	100.00	100.00			100.00	100.00
u_prim_arbiter_ppc_packer_arb	95.16	95.00	92.31			100.00	93.33
u_prim_count_max_reqs_cntr	17.82			17.82
u_prim_edge_detector_recov_alert	100.00	100.00	100.00			100.00
u_prim_fifo_sync_gencmd	96.15	100.00	84.62			100.00	100.00
u_prim_fifo_sync_rescmd	97.12	100.00	88.46			100.00	100.00
u_prim_mubi4_sync_auto_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_boot_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_cmd_fifo_rst	100.00	100.00					100.00
u_prim_mubi4_sync_edn_enable	100.00	100.00					100.00
u_prim_packer_fifo_cs	95.24	100.00	95.24			85.71	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
TOTAL		229	229	100.00
ALWAYS	204	27	27	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	275	1	1	100.00
CONT_ASSIGN	280	1	1	100.00
CONT_ASSIGN	286	1	1	100.00
CONT_ASSIGN	288	1	1	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	294	1	1	100.00
CONT_ASSIGN	297	1	1	100.00
CONT_ASSIGN	301	1	1	100.00
CONT_ASSIGN	305	1	1	100.00
CONT_ASSIGN	313	1	1	100.00
CONT_ASSIGN	316	1	1	100.00
CONT_ASSIGN	319	1	1	100.00
CONT_ASSIGN	322	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	327	1	1	100.00
CONT_ASSIGN	328	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	344	1	1	100.00
CONT_ASSIGN	349	1	1	100.00
CONT_ASSIGN	368	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	375	1	1	100.00
CONT_ASSIGN	384	1	1	100.00
CONT_ASSIGN	385	1	1	100.00
CONT_ASSIGN	386	1	1	100.00
CONT_ASSIGN	387	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	390	1	1	100.00
CONT_ASSIGN	405	1	1	100.00
CONT_ASSIGN	406	1	1	100.00
CONT_ASSIGN	407	1	1	100.00
CONT_ASSIGN	408	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	425	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	434	1	1	100.00
CONT_ASSIGN	435	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	451	1	1	100.00
CONT_ASSIGN	452	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	455	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	463	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	468	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	484	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	504	1	1	100.00
CONT_ASSIGN	512	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	519	1	1	100.00
CONT_ASSIGN	523	1	1	100.00
CONT_ASSIGN	533	1	1	100.00
CONT_ASSIGN	534	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	545	1	1	100.00
CONT_ASSIGN	552	1	1	100.00
CONT_ASSIGN	553	1	1	100.00
CONT_ASSIGN	580	1	1	100.00
CONT_ASSIGN	582	1	1	100.00
CONT_ASSIGN	586	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	592	1	1	100.00
CONT_ASSIGN	594	1	1	100.00
CONT_ASSIGN	620	1	1	100.00
CONT_ASSIGN	622	1	1	100.00
CONT_ASSIGN	626	1	1	100.00
CONT_ASSIGN	630	1	1	100.00
CONT_ASSIGN	632	1	1	100.00
CONT_ASSIGN	634	1	1	100.00
CONT_ASSIGN	691	1	1	100.00
CONT_ASSIGN	695	1	1	100.00
CONT_ASSIGN	698	1	1	100.00
CONT_ASSIGN	708	1	1	100.00
CONT_ASSIGN	713	1	1	100.00
CONT_ASSIGN	714	1	1	100.00
CONT_ASSIGN	715	1	1	100.00
CONT_ASSIGN	716	1	1	100.00
CONT_ASSIGN	719	1	1	100.00
CONT_ASSIGN	755	1	1	100.00
CONT_ASSIGN	755	1	1	100.00
CONT_ASSIGN	755	1	1	100.00
CONT_ASSIGN	755	1	1	100.00
CONT_ASSIGN	755	1	1	100.00
CONT_ASSIGN	755	1	1	100.00
CONT_ASSIGN	755	1	1	100.00
CONT_ASSIGN	779	1	1	100.00
CONT_ASSIGN	780	1	1	100.00
CONT_ASSIGN	781	1	1	100.00
CONT_ASSIGN	782	1	1	100.00
CONT_ASSIGN	783	1	1	100.00
CONT_ASSIGN	784	1	1	100.00
CONT_ASSIGN	786	1	1	100.00
CONT_ASSIGN	801	1	1	100.00
CONT_ASSIGN	803	1	1	100.00
CONT_ASSIGN	805	1	1	100.00
CONT_ASSIGN	811	1	1	100.00
CONT_ASSIGN	814	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	850	1	1	100.00
CONT_ASSIGN	870	1	1	100.00
CONT_ASSIGN	876	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
209	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
270	1	1
275	1	1
280	1	1
286	1	1
288	1	1
290	1	1
292	1	1
294	1	1
297	1	1
301	1	1
305	1	1
313	1	1
316	1	1
319	1	1
322	1	1
325	1	1
327	1	1
328	1	1
333	1	1
336	1	1
339	1	1
344	31	31
349	1	1
368	1	1
371	1	1
375	1	1
384	1	1
385	1	1
386	1	1
387	1	1
390	17	17
405	1	1
406	1	1
407	1	1
408	1	1
411	3	3
425	1	1
432	1	1
433	1	1
434	1	1
435	1	1
436	1	1
451	1	1
452	1	1
454	1	1
455	1	1
457	1	1
458	1	1
460	1	1
461	1	1
463	1	1
464	1	1
465	1	1
468	1	1
477	1	1
484	1	1
488	1	1
504	1	1
512	1	1
513	1	1
518	1	1
519	1	1
523	1	1
533	1	1
534	1	1
544	1	1
545	1	1
552	1	1
553	1	1
580	1	1
582	1	1
586	1	1
590	1	1
592	1	1
594	1	1
620	1	1
622	1	1
626	1	1
630	1	1
632	1	1
634	1	1
691	1	1
695	1	1
698	1	1
708	1	1
713	1	1
714	1	1
715	1	1
716	1	1
719	1	1
755	7	7
779	1	1
780	1	1
781	1	1
782	1	1
783	1	1
784	1	1
786	1	1
801	1	1
803	1	1
805	1	1
811	1	1
814	1	1
815	1	1
839	7	7
840	7	7
843	7	7
846	7	7
849	7	7
850	7	7
870	1	1
876	1	1

---

Cond Coverage for Module : edn_core

	Total	Covered	Percent
Conditions	554	497	89.71
Logical	554	497	89.71
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
270-786	92.29
786-876	78.00

---

Branch Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
Branches		86	86	100.00
TERNARY	468	6	6	100.00
TERNARY	477	4	4	100.00
TERNARY	488	7	7	100.00
TERNARY	504	5	5	100.00
TERNARY	523	6	6	100.00
TERNARY	534	6	6	100.00
TERNARY	545	3	3	100.00
TERNARY	553	4	4	100.00
TERNARY	582	2	2	100.00
TERNARY	586	2	2	100.00
TERNARY	622	2	2	100.00
TERNARY	626	2	2	100.00
TERNARY	698	6	6	100.00
TERNARY	786	3	3	100.00
TERNARY	803	2	2	100.00
TERNARY	805	3	3	100.00
TERNARY	843	3	3	100.00
TERNARY	843	3	3	100.00
TERNARY	843	3	3	100.00
TERNARY	843	3	3	100.00
TERNARY	843	3	3	100.00
TERNARY	843	3	3	100.00
TERNARY	843	3	3	100.00
IF	204	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	468	((!edn_enable_fo[CsrngCmdReq])) ? 
-2-:	468	(boot_wr_ins_cmd) ? 
-3-:	468	(boot_wr_gen_cmd) ? 
-4-:	468	(boot_wr_uni_cmd) ? 
-5-:	468	(sw_cmd_req_load) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T28,T37,T31
0	0	1	-	-	Covered	T28,T37,T31
0	0	0	1	-	Covered	T28,T31,T78
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	477	((!edn_enable_fo[CsrngCmdReqValid])) ? 
-2-:	477	(cs_cmd_handshake) ? 
-3-:	477	((((sw_cmd_req_load || boot_wr_ins_cmd) || boot_wr_gen_cmd) || boot_wr_uni_cmd)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	488	((!edn_enable_fo[CsrngCmdReqOut])) ? 
-2-:	488	((send_rescmd || capt_rescmd_fifo_cnt)) ? 
-3-:	488	(sfifo_rescmd_pop) ? 
-4-:	488	((send_gencmd || capt_gencmd_fifo_cnt)) ? 
-5-:	488	(sfifo_gencmd_pop) ? 
-6-:	488	((cs_cmd_req_vld_q && (!cs_cmd_handshake))) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	Covered	T7,T8,T29
0	1	0	-	-	-	Covered	T7,T8,T29
0	0	-	1	1	-	Covered	T2,T7,T8
0	0	-	1	0	-	Covered	T2,T7,T8
0	0	-	0	-	1	Covered	T1,T2,T3
0	0	-	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	504	((!edn_enable_fo[CsrngCmdReqValidOut])) ? 
-2-:	504	(cmd_sent) ? 
-3-:	504	((send_rescmd || capt_rescmd_fifo_cnt)) ? 
-4-:	504	((send_gencmd || capt_gencmd_fifo_cnt)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T2,T7,T8
0	0	1	-	Covered	T7,T8,T29
0	0	0	1	Covered	T2,T7,T8
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	523	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	523	((!sw_cmd_valid)) ? 
-3-:	523	(sw_cmd_req_load) ? 
-4-:	523	(accept_sw_cmds_pulse) ? 
-5-:	523	(csrng_cmd_i.csrng_rsp_ack) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T3,T7
0	0	1	-	-	Covered	T1,T2,T3
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	534	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	534	((!sw_cmd_valid)) ? 
-3-:	534	(sw_cmd_req_load) ? 
-4-:	534	(accept_sw_cmds_pulse) ? 
-5-:	534	(cs_cmd_handshake) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T3,T7
0	0	1	-	-	Covered	T1,T2,T3
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	545	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	545	((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	553	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	553	(sw_cmd_req_load) ? 
-3-:	553	((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	582	(rescmd_handshake) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T29
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	586	(auto_req_mode_busy) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	622	(gencmd_handshake) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	626	(auto_req_mode_busy) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	698	((!edn_enable_fo[CmdFifoCnt])) ? 
-2-:	698	((cmd_fifo_rst_fo[3] || main_sm_done_pulse)) ? 
-3-:	698	(capt_gencmd_fifo_cnt) ? 
-4-:	698	(capt_rescmd_fifo_cnt) ? 
-5-:	698	((sfifo_gencmd_pop || sfifo_rescmd_pop)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T3,T28
0	0	1	-	-	Covered	T2,T7,T8
0	0	0	1	-	Covered	T7,T8,T29
0	0	0	0	1	Covered	T7,T8,T29
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	786	((!edn_enable_fo[CsrngFipsEn])) ? 
-2-:	786	((packer_cs_push && packer_cs_wready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	803	(cs_rdata_capt_vld) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	805	((!edn_enable_fo[CsrngDataVld])) ? 
-2-:	805	(cs_rdata_capt_vld) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	843	(packer_ep_clr[0]) ? 
-2-:	843	((packer_ep_push[0] && packer_ep_wready[0])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T7,T31
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	843	(packer_ep_clr[1]) ? 
-2-:	843	((packer_ep_push[1] && packer_ep_wready[1])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T28,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	843	(packer_ep_clr[2]) ? 
-2-:	843	((packer_ep_push[2] && packer_ep_wready[2])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T7,T29
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	843	(packer_ep_clr[3]) ? 
-2-:	843	((packer_ep_push[3] && packer_ep_wready[3])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T3,T29
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	843	(packer_ep_clr[4]) ? 
-2-:	843	((packer_ep_push[4] && packer_ep_wready[4])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T28,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	843	(packer_ep_clr[5]) ? 
-2-:	843	((packer_ep_push[5] && packer_ep_wready[5])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T29,T30
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	843	(packer_ep_clr[6]) ? 
-2-:	843	((packer_ep_push[6] && packer_ep_wready[6])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T28
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	204	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3