Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	754174	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

6348950

1

T1

4

T2

9

T3

58

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1855892	1			T1	1		T2	62		T3	122
values[0x0]	2422782	1			T1	3		T2	6		T3	30
values[0x1]	2824450	1			T1	1		T2	1		T3	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	363343	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6739781

1

T1

4

T2

29

T3

107

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	27182	1			T3	1		T4	626		T33	3
valid_sources[0x01]	27852	1			T3	1		T10	1		T4	651
valid_sources[0x02]	26354	1			T4	630		T5	276		T41	1
valid_sources[0x03]	27710	1			T4	576		T5	154		T28	2
valid_sources[0x04]	29503	1			T3	1		T10	2		T4	637
valid_sources[0x05]	28201	1			T10	1		T4	651		T25	1
valid_sources[0x06]	28722	1			T4	648		T26	1		T5	314
valid_sources[0x07]	27294	1			T3	2		T4	609		T25	3
valid_sources[0x08]	27009	1			T4	593		T5	200		T12	2
valid_sources[0x09]	27865	1			T4	636		T26	1		T5	115
valid_sources[0x0a]	29408	1			T4	628		T5	235		T28	4
valid_sources[0x0b]	26897	1			T4	684		T5	315		T28	1
valid_sources[0x0c]	29347	1			T3	4		T11	299		T4	593
valid_sources[0x0d]	28288	1			T4	628		T26	3		T5	122
valid_sources[0x0e]	28579	1			T4	578		T5	309		T28	1
valid_sources[0x0f]	27828	1			T3	1		T4	605		T26	2
valid_sources[0x10]	28109	1			T3	1		T10	4		T4	608
valid_sources[0x11]	26923	1			T4	637		T5	313		T28	3
valid_sources[0x12]	26644	1			T3	3		T4	644		T5	109
valid_sources[0x13]	28409	1			T4	659		T26	2		T5	371
valid_sources[0x14]	27399	1			T10	1		T4	594		T5	241
valid_sources[0x15]	26017	1			T4	632		T25	8		T5	222
valid_sources[0x16]	27677	1			T3	2		T10	1		T4	656
valid_sources[0x17]	26772	1			T4	619		T5	269		T28	1
valid_sources[0x18]	29171	1			T4	669		T5	230		T28	1
valid_sources[0x19]	27824	1			T10	1		T4	658		T5	238
valid_sources[0x1a]	26858	1			T10	4		T4	638		T25	1
valid_sources[0x1b]	26742	1			T4	633		T5	169		T23	1
valid_sources[0x1c]	25927	1			T4	618		T5	276		T29	3
valid_sources[0x1d]	26183	1			T4	612		T5	199		T28	8
valid_sources[0x1e]	28512	1			T3	2		T4	616		T5	196
valid_sources[0x1f]	26983	1			T3	2		T4	673		T5	274
valid_sources[0x20]	26439	1			T4	682		T25	1		T26	3
valid_sources[0x21]	26959	1			T3	2		T4	613		T5	104
valid_sources[0x22]	28907	1			T4	654		T5	108		T28	2
valid_sources[0x23]	27502	1			T4	651		T5	320		T24	356
valid_sources[0x24]	26722	1			T3	2		T10	1		T4	637
valid_sources[0x25]	29295	1			T4	579		T26	1		T5	208
valid_sources[0x26]	27914	1			T4	644		T5	300		T12	2
valid_sources[0x27]	29137	1			T3	2		T4	660		T26	1
valid_sources[0x28]	26494	1			T4	607		T5	194		T28	1
valid_sources[0x29]	28721	1			T4	602		T5	268		T12	1
valid_sources[0x2a]	27401	1			T4	578		T5	367		T28	1
valid_sources[0x2b]	28108	1			T3	6		T10	1		T4	639
valid_sources[0x2c]	27746	1			T3	4		T10	4		T4	634
valid_sources[0x2d]	27320	1			T4	691		T5	123		T24	274
valid_sources[0x2e]	27240	1			T4	697		T5	240		T24	314
valid_sources[0x2f]	24632	1			T3	1		T10	1		T4	642
valid_sources[0x30]	28259	1			T4	678		T26	1		T5	295
valid_sources[0x31]	27521	1			T3	1		T4	633		T25	4
valid_sources[0x32]	27584	1			T3	8		T4	674		T5	305
valid_sources[0x33]	28563	1			T3	1		T4	607		T26	1
valid_sources[0x34]	27905	1			T10	1		T4	590		T25	1
valid_sources[0x35]	28235	1			T3	1		T4	645		T26	1
valid_sources[0x36]	29224	1			T3	1		T4	661		T5	214
valid_sources[0x37]	27782	1			T4	651		T5	269		T12	1
valid_sources[0x38]	27769	1			T4	659		T5	313		T12	2
valid_sources[0x39]	26161	1			T4	686		T5	207		T28	1
valid_sources[0x3a]	28164	1			T4	629		T26	3		T5	207
valid_sources[0x3b]	28681	1			T10	3		T4	663		T26	1
valid_sources[0x3c]	27610	1			T4	620		T26	2		T5	217
valid_sources[0x3d]	27766	1			T3	2		T10	1		T4	614
valid_sources[0x3e]	26447	1			T4	625		T5	162		T41	1
valid_sources[0x3f]	26724	1			T4	649		T5	248		T18	1
valid_sources[0x40]	24971	1			T4	584		T5	205		T12	1
valid_sources[0x41]	26793	1			T4	627		T5	87		T12	1
valid_sources[0x42]	26775	1			T4	632		T5	222		T28	3
valid_sources[0x43]	28932	1			T3	1		T4	700		T25	1
valid_sources[0x44]	26577	1			T10	1		T4	687		T5	362
valid_sources[0x45]	27891	1			T10	3		T4	630		T5	406
valid_sources[0x46]	28181	1			T3	4		T4	652		T5	184
valid_sources[0x47]	26800	1			T4	659		T25	2		T5	277
valid_sources[0x48]	28204	1			T4	708		T5	211		T28	1
valid_sources[0x49]	27595	1			T4	703		T5	195		T28	1
valid_sources[0x4a]	28044	1			T4	657		T5	325		T28	1
valid_sources[0x4b]	28022	1			T4	626		T25	3		T5	311
valid_sources[0x4c]	26814	1			T3	1		T4	636		T25	3
valid_sources[0x4d]	26488	1			T4	605		T5	348		T29	1
valid_sources[0x4e]	26609	1			T32	1		T4	664		T5	255
valid_sources[0x4f]	27658	1			T10	1		T4	641		T5	184
valid_sources[0x50]	27480	1			T3	3		T10	3		T4	589
valid_sources[0x51]	27601	1			T4	691		T5	263		T29	2
valid_sources[0x52]	28214	1			T3	2		T4	645		T25	2
valid_sources[0x53]	25437	1			T3	3		T4	644		T5	113
valid_sources[0x54]	30318	1			T3	5		T4	678		T5	155
valid_sources[0x55]	28348	1			T3	9		T10	1		T4	645
valid_sources[0x56]	28839	1			T3	5		T10	1		T4	689
valid_sources[0x57]	28586	1			T4	629		T5	219		T28	6
valid_sources[0x58]	29243	1			T4	655		T5	108		T28	5
valid_sources[0x59]	27956	1			T3	1		T4	633		T5	134
valid_sources[0x5a]	28687	1			T3	1		T10	1		T4	605
valid_sources[0x5b]	28192	1			T4	630		T26	3		T5	239
valid_sources[0x5c]	27138	1			T10	1		T4	641		T5	237
valid_sources[0x5d]	26644	1			T10	1		T4	619		T26	2
valid_sources[0x5e]	25485	1			T10	3		T4	671		T5	230
valid_sources[0x5f]	29538	1			T4	638		T25	3		T5	274
valid_sources[0x60]	26821	1			T4	648		T5	219		T28	1
valid_sources[0x61]	26847	1			T4	602		T26	2		T5	127
valid_sources[0x62]	27699	1			T4	598		T5	287		T12	1
valid_sources[0x63]	27779	1			T4	631		T26	2		T5	243
valid_sources[0x64]	28569	1			T10	1		T4	661		T5	201
valid_sources[0x65]	27585	1			T4	611		T5	232		T28	3
valid_sources[0x66]	27018	1			T10	2		T4	660		T5	250
valid_sources[0x67]	27382	1			T4	629		T5	217		T24	298
valid_sources[0x68]	27764	1			T4	691		T25	1		T5	112
valid_sources[0x69]	28909	1			T4	626		T26	1		T5	167
valid_sources[0x6a]	26684	1			T3	2		T10	1		T4	670
valid_sources[0x6b]	27781	1			T10	3		T4	663		T5	154
valid_sources[0x6c]	28451	1			T3	3		T10	1		T4	641
valid_sources[0x6d]	27520	1			T3	1		T10	1		T4	696
valid_sources[0x6e]	28292	1			T4	652		T5	232		T29	2
valid_sources[0x6f]	28964	1			T10	1		T4	656		T26	1
valid_sources[0x70]	26483	1			T10	1		T4	643		T5	240
valid_sources[0x71]	26465	1			T3	1		T4	665		T26	2
valid_sources[0x72]	28507	1			T10	1		T32	1		T4	633
valid_sources[0x73]	27132	1			T1	2		T4	659		T5	202
valid_sources[0x74]	27526	1			T10	1		T4	648		T5	152
valid_sources[0x75]	26669	1			T4	641		T5	42		T12	1
valid_sources[0x76]	28369	1			T10	6		T4	662		T25	1
valid_sources[0x77]	26693	1			T10	2		T4	653		T25	1
valid_sources[0x78]	26547	1			T3	7		T4	613		T5	263
valid_sources[0x79]	28764	1			T4	633		T5	214		T29	1
valid_sources[0x7a]	28670	1			T3	2		T10	2		T4	641
valid_sources[0x7b]	28632	1			T4	682		T26	2		T5	215
valid_sources[0x7c]	27234	1			T3	1		T4	593		T25	1
valid_sources[0x7d]	27841	1			T3	4		T4	660		T5	296
valid_sources[0x7e]	27507	1			T3	1		T4	618		T5	229
valid_sources[0x7f]	27188	1			T10	1		T4	651		T5	221
valid_sources[0x80]	26715	1			T10	2		T4	690		T26	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1596662

1

T1

1

T2

5

T3

3

values[0x0]

all_enables

biggest_size

2376191

1

T1

2

T2

4

T3

29

values[0x1]

all_enables

biggest_size

2376097

1

T1

1

T3

26

T10

34