Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2561	1			T3	4		T10	1		T11	2
non_zero_bins[1]	1915	1			T3	3		T10	2		T11	1
zero	8402	1			T1	2		T2	3		T3	1

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	486	1			T4	12		T25	1		T5	5
uni	3576	1			T2	1		T3	1		T4	78
gen	3865	1			T1	1		T2	1		T3	4
res	855	1			T3	2		T10	1		T11	2
ins	4096	1			T1	1		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8671

1

T1

1

T2

2

T3

2

mubi_true

4207

1

T1

1

T2

1

T3

6

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T18

1

T19

1

T20

1

pass

12828

1

T1

2

T2

3

T3

8

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	128	1			T4	1		T24	2		T129	2
upd	non_zero_bins[0]	pass	mubi_true	105	1			T4	1		T5	1		T129	2
upd	non_zero_bins[1]	pass	mubi_false	88	1			T4	4		T5	2		T24	1
upd	non_zero_bins[1]	pass	mubi_true	83	1			T4	3		T5	2		T24	1
upd	zero	pass	mubi_false	37	1			T4	1		T24	2		T130	3
upd	zero	pass	mubi_true	45	1			T4	2		T25	1		T24	1
uni	zero	fail	mubi_false	10	1			T111	1		T112	1		T113	1
uni	zero	pass	mubi_false	2626	1			T3	1		T4	54		T25	2
uni	zero	pass	mubi_true	940	1			T2	1		T4	24		T5	7
gen	non_zero_bins[0]	pass	mubi_false	445	1			T11	2		T4	4		T25	1
gen	non_zero_bins[0]	pass	mubi_true	456	1			T3	3		T4	11		T5	4
gen	non_zero_bins[1]	pass	mubi_false	339	1			T3	1		T4	5		T5	2
gen	non_zero_bins[1]	pass	mubi_true	378	1			T4	8		T5	3		T52	3
gen	zero	fail	mubi_false	28	1			T18	1		T20	1		T57	1
gen	zero	pass	mubi_false	1778	1			T1	1		T2	1		T32	2
gen	zero	pass	mubi_true	441	1			T4	3		T5	2		T23	2
res	non_zero_bins[0]	pass	mubi_false	184	1			T4	4		T5	1		T12	2
res	non_zero_bins[0]	pass	mubi_true	202	1			T4	7		T26	2		T40	6
res	non_zero_bins[1]	pass	mubi_false	129	1			T10	1		T4	2		T52	2
res	non_zero_bins[1]	pass	mubi_true	124	1			T3	2		T28	2		T47	2
res	zero	fail	mubi_false	8	1			T19	1		T140	1		T133	1
res	zero	pass	mubi_false	105	1			T43	2		T46	2		T129	1
res	zero	pass	mubi_true	103	1			T11	2		T4	1		T5	1
ins	non_zero_bins[0]	pass	mubi_false	523	1			T10	1		T4	8		T5	5
ins	non_zero_bins[0]	pass	mubi_true	518	1			T3	1		T4	21		T25	1
ins	non_zero_bins[1]	pass	mubi_false	377	1			T4	4		T26	1		T5	2
ins	non_zero_bins[1]	pass	mubi_true	397	1			T10	1		T11	1		T4	5
ins	zero	fail	mubi_false	4	1			T91	1		T92	1		T93	1
ins	zero	pass	mubi_false	1862	1			T2	1		T4	36		T25	1
ins	zero	pass	mubi_true	415	1			T1	1		T32	2		T4	4

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded