Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	240443549	11321513	0	0
boot_gen_cmd_rd_A	240443549	42374	0	0
boot_ins_cmd_rd_A	240443549	47823	0	0
ctrl_rd_A	240443549	42903	0	0
err_code_test_rd_A	240443549	47926	0	0
intr_enable_rd_A	240443549	47946	0	0
max_num_reqs_between_reseeds_rd_A	240443549	42317	0	0
regwen_rd_A	240443549	48592	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240443549	11321513	0	0
T4	468326	259090	0	0
T5	165764	95183	0	0
T6	1551	0	0	0
T23	1390	0	0	0
T24	0	121021	0	0
T25	2298	0	0	0
T26	5631	0	0	0
T27	5887	0	0	0
T28	6574	0	0	0
T33	1055	0	0	0
T51	1724	0	0	0
T129	0	102340	0	0
T130	0	241494	0	0
T173	0	127150	0	0
T174	0	193622	0	0
T175	0	367890	0	0
T176	0	332722	0	0
T177	0	455271	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240443549	42374	0	0
T81	488	0	0	0
T86	942	0	0	0
T87	1049	0	0	0
T88	3124	0	0	0
T100	605	0	0	0
T149	1392	0	0	0
T178	452292	4613	0	0
T179	0	2901	0	0
T180	0	1701	0	0
T181	0	1680	0	0
T182	0	1751	0	0
T183	0	1934	0	0
T184	0	942	0	0
T185	0	8632	0	0
T186	0	6314	0	0
T187	0	3643	0	0
T188	3470	0	0	0
T189	5513	0	0	0
T190	8231	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240443549	47823	0	0
T81	488	0	0	0
T86	942	0	0	0
T87	1049	0	0	0
T88	3124	0	0	0
T100	605	0	0	0
T149	1392	0	0	0
T178	452292	5310	0	0
T179	0	3123	0	0
T180	0	2040	0	0
T181	0	1832	0	0
T182	0	1848	0	0
T183	0	2436	0	0
T184	0	1320	0	0
T185	0	9696	0	0
T186	0	7121	0	0
T187	0	4053	0	0
T188	3470	0	0	0
T189	5513	0	0	0
T190	8231	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240443549	42903	0	0
T65	0	5	0	0
T82	0	6	0	0
T94	1197	0	0	0
T133	2168	0	0	0
T152	2190	0	0	0
T174	468902	0	0	0
T178	0	4821	0	0
T179	0	3015	0	0
T180	0	1962	0	0
T181	0	1466	0	0
T182	0	1736	0	0
T191	1041	4	0	0
T192	0	1	0	0
T193	0	6	0	0
T194	5972	0	0	0
T195	2274	0	0	0
T196	2731	0	0	0
T197	2664	0	0	0
T198	1860	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240443549	47926	0	0
T81	488	0	0	0
T86	942	0	0	0
T87	1049	0	0	0
T88	3124	0	0	0
T100	605	0	0	0
T149	1392	0	0	0
T178	452292	5296	0	0
T179	0	3248	0	0
T180	0	2139	0	0
T181	0	1831	0	0
T182	0	1946	0	0
T183	0	2232	0	0
T184	0	1356	0	0
T185	0	9570	0	0
T186	0	7176	0	0
T187	0	4241	0	0
T188	3470	0	0	0
T189	5513	0	0	0
T190	8231	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240443549	47946	0	0
T57	2004	0	0	0
T164	3606	0	0	0
T178	0	5401	0	0
T179	0	3078	0	0
T180	0	1950	0	0
T181	0	1570	0	0
T199	14868	35	0	0
T200	0	53	0	0
T201	0	34	0	0
T202	0	68	0	0
T203	0	121	0	0
T204	0	49	0	0
T205	1856	0	0	0
T206	876	0	0	0
T207	2285	0	0	0
T208	2161	0	0	0
T209	4476	0	0	0
T210	3632	0	0	0
T211	2761	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240443549	42317	0	0
T81	488	0	0	0
T86	942	0	0	0
T87	1049	0	0	0
T88	3124	0	0	0
T100	605	0	0	0
T149	1392	0	0	0
T178	452292	4846	0	0
T179	0	2857	0	0
T180	0	1724	0	0
T181	0	1504	0	0
T182	0	1579	0	0
T183	0	2305	0	0
T184	0	1078	0	0
T185	0	8398	0	0
T186	0	6082	0	0
T187	0	3665	0	0
T188	3470	0	0	0
T189	5513	0	0	0
T190	8231	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	240443549	48592	0	0
T81	488	0	0	0
T86	942	0	0	0
T87	1049	0	0	0
T88	3124	0	0	0
T100	605	0	0	0
T149	1392	0	0	0
T178	452292	5241	0	0
T179	0	3188	0	0
T180	0	1896	0	0
T181	0	1886	0	0
T182	0	1855	0	0
T183	0	2223	0	0
T184	0	1332	0	0
T185	0	9621	0	0
T186	0	7391	0	0
T187	0	4104	0	0
T188	3470	0	0	0
T189	5513	0	0	0
T190	8231	0	0	0