Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.15 100.00 84.62 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.15 100.00 84.62 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.12 100.00 88.46 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_normal_fifo.u_fifo_cnt 100.00 100.00 100.00

Line Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Module : prim_fifo_sync
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T10,T11

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT3,T10,T11
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT3,T10,T11
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT121
110Not Covered
111CoveredT3,T10,T11

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT117,T118,T119
101CoveredT3,T10,T11
110Not Covered
111CoveredT3,T10,T11

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T10,T11

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T10,T11

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T10,T11
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 88 3 3 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T3,T10,T11
0 1 Covered T1,T2,T3
0 0 Covered T3,T10,T11


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T10,T11


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T10,T11
0 Covered T1,T2,T3


Assert Coverage for Module : prim_fifo_sync
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 479547462 1000627 0 0
DepthKnown_A 479914320 479600404 0 0
RvalidKnown_A 479914320 479600404 0 0
WreadyKnown_A 479914320 479600404 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 479914320 1089952 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 479547462 1000627 0 0
T3 6444 2542 0 0
T4 936652 0 0 0
T5 331528 0 0 0
T6 206 0 0 0
T10 6950 4203 0 0
T11 9560 6556 0 0
T12 0 1370 0 0
T25 4596 0 0 0
T26 11262 8344 0 0
T27 0 8352 0 0
T28 0 8367 0 0
T32 1576 0 0 0
T33 2110 0 0 0
T40 0 3976 0 0
T41 0 2634 0 0
T52 0 1458 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 479914320 479600404 0 0
T1 2792 2682 0 0
T2 2314 2214 0 0
T3 6444 6262 0 0
T4 936652 936626 0 0
T10 6950 6776 0 0
T11 9560 9380 0 0
T25 4596 4424 0 0
T26 11262 11144 0 0
T32 1576 1376 0 0
T33 2110 1942 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 479914320 479600404 0 0
T1 2792 2682 0 0
T2 2314 2214 0 0
T3 6444 6262 0 0
T4 936652 936626 0 0
T10 6950 6776 0 0
T11 9560 9380 0 0
T25 4596 4424 0 0
T26 11262 11144 0 0
T32 1576 1376 0 0
T33 2110 1942 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 479914320 479600404 0 0
T1 2792 2682 0 0
T2 2314 2214 0 0
T3 6444 6262 0 0
T4 936652 936626 0 0
T10 6950 6776 0 0
T11 9560 9380 0 0
T25 4596 4424 0 0
T26 11262 11144 0 0
T32 1576 1376 0 0
T33 2110 1942 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 479914320 1089952 0 0
T3 6444 2542 0 0
T4 936652 0 0 0
T5 331528 0 0 0
T6 3102 220 0 0
T10 6950 4203 0 0
T11 9560 6556 0 0
T15 0 2292 0 0
T23 0 338 0 0
T25 4596 0 0 0
T26 11262 8344 0 0
T27 0 8352 0 0
T28 0 8367 0 0
T32 1576 0 0 0
T33 2110 0 0 0
T52 0 1458 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalCoveredPercent
Conditions262284.62
Logical262284.62
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T52,T36

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT3,T10,T26
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT3,T10,T26
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110Not Covered
111CoveredT3,T10,T11

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT117,T118,T119
101CoveredT3,T10,T11
110Not Covered
111CoveredT3,T10,T11

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT28,T52,T36
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T10,T11

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT28,T52,T36

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T10,T11
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 88 3 3 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T28,T52,T36
0 1 Covered T1,T2,T3
0 0 Covered T3,T10,T26


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T10,T11


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T10,T11
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 239773731 495362 0 0
DepthKnown_A 239957160 239800202 0 0
RvalidKnown_A 239957160 239800202 0 0
WreadyKnown_A 239957160 239800202 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 239957160 539735 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239773731 495362 0 0
T3 3222 1268 0 0
T4 468326 0 0 0
T5 165764 0 0 0
T6 103 0 0 0
T10 3475 2056 0 0
T11 4780 3264 0 0
T12 0 652 0 0
T25 2298 0 0 0
T26 5631 4128 0 0
T27 0 4163 0 0
T28 0 4196 0 0
T32 788 0 0 0
T33 1055 0 0 0
T40 0 1899 0 0
T41 0 1309 0 0
T52 0 733 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239957160 239800202 0 0
T1 1396 1341 0 0
T2 1157 1107 0 0
T3 3222 3131 0 0
T4 468326 468313 0 0
T10 3475 3388 0 0
T11 4780 4690 0 0
T25 2298 2212 0 0
T26 5631 5572 0 0
T32 788 688 0 0
T33 1055 971 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239957160 239800202 0 0
T1 1396 1341 0 0
T2 1157 1107 0 0
T3 3222 3131 0 0
T4 468326 468313 0 0
T10 3475 3388 0 0
T11 4780 4690 0 0
T25 2298 2212 0 0
T26 5631 5572 0 0
T32 788 688 0 0
T33 1055 971 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239957160 239800202 0 0
T1 1396 1341 0 0
T2 1157 1107 0 0
T3 3222 3131 0 0
T4 468326 468313 0 0
T10 3475 3388 0 0
T11 4780 4690 0 0
T25 2298 2212 0 0
T26 5631 5572 0 0
T32 788 688 0 0
T33 1055 971 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 239957160 539735 0 0
T3 3222 1268 0 0
T4 468326 0 0 0
T5 165764 0 0 0
T6 1551 111 0 0
T10 3475 2056 0 0
T11 4780 3264 0 0
T15 0 1148 0 0
T23 0 171 0 0
T25 2298 0 0 0
T26 5631 4128 0 0
T27 0 4163 0 0
T28 0 4196 0 0
T32 788 0 0 0
T33 1055 0 0 0
T52 0 733 0 0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
TOTAL2222100.00
ALWAYS7044100.00
CONT_ASSIGN8411100.00
CONT_ASSIGN8511100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN8711100.00
CONT_ASSIGN8811100.00
CONT_ASSIGN9211100.00
CONT_ASSIGN9311100.00
CONT_ASSIGN9811100.00
CONT_ASSIGN9911100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN14511100.00
CONT_ASSIGN14611100.00
CONT_ASSIGN16211100.00
ALWAYS16522100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN17611100.00
CONT_ASSIGN18011100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
70 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
84 1 1
85 1 1
86 1 1
87 1 1
88 1 1
92 1 1
93 1 1
98 1 1
99 1 1
100 1 1
145 1 1
146 1 1
162 1 1
165 1 1
166 1 1
MISSING_ELSE
175 1 1
176 1 1
180 1 1


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalCoveredPercent
Conditions262388.46
Logical262388.46
Non-Logical00
Event00

 LINE       88
 EXPRESSION 
 Number  Term
      1  gen_normal_fifo.full ? (4'(Depth)) : ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value)))))
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T10,T11

 LINE       88
 SUB-EXPRESSION 
 Number  Term
      1  (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb) ? ((4'(gen_normal_fifo.wptr_value) - 4'(gen_normal_fifo.rptr_value))) : (((4'(Depth) - 4'(gen_normal_fifo.rptr_value)) + 4'(gen_normal_fifo.wptr_value))))
-1-StatusTests
0CoveredT3,T10,T11
1CoveredT1,T2,T3

 LINE       88
 SUB-EXPRESSION (gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)
                ---------------------------1--------------------------
-1-StatusTests
0CoveredT3,T10,T11
1CoveredT1,T2,T3

 LINE       92
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT121
110Not Covered
111CoveredT3,T10,T11

 LINE       93
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------
-1--2--3-StatusTests
011CoveredT122,T125
101CoveredT3,T10,T11
110Not Covered
111CoveredT3,T10,T11

 LINE       98
 EXPRESSION (((~gen_normal_fifo.full)) & ((~gen_normal_fifo.under_rst)))
             ------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT3,T10,T11
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       100
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T10,T11

 LINE       145
 EXPRESSION (gen_normal_fifo.fifo_wptr == (gen_normal_fifo.fifo_rptr ^ {1'b1, {(gen_normal_fifo.PTR_WIDTH - 1) {1'b0}}}))
            ------------------------------------------------------1------------------------------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T10,T11

 LINE       146
 EXPRESSION (gen_normal_fifo.fifo_wptr == gen_normal_fifo.fifo_rptr)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       180
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------
-1-StatusTests
0CoveredT3,T10,T11
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
Line No.TotalCoveredPercent
Branches 10 10 100.00
TERNARY 88 3 3 100.00
TERNARY 180 2 2 100.00
IF 70 3 3 100.00
IF 165 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 88 (gen_normal_fifo.full) ? -2-: 88 ((gen_normal_fifo.wptr_msb == gen_normal_fifo.rptr_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T3,T10,T11
0 1 Covered T1,T2,T3
0 0 Covered T3,T10,T11


LineNo. Expression -1-: 180 (gen_normal_fifo.empty) ?

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T3,T10,T11


LineNo. Expression -1-: 70 if ((!rst_ni)) -2-: 72 if (gen_normal_fifo.under_rst)

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T1,T2,T3
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 165 if (gen_normal_fifo.fifo_incr_wptr)

Branches:
-1-StatusTests
1 Covered T3,T10,T11
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 5 5 100.00 5 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 5 5 100.00 5 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DataKnown_A 239773731 505265 0 0
DepthKnown_A 239957160 239800202 0 0
RvalidKnown_A 239957160 239800202 0 0
WreadyKnown_A 239957160 239800202 0 0
gen_normal_fifo.depthShallNotExceedParamDepth 239957160 550217 0 0


DataKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239773731 505265 0 0
T3 3222 1274 0 0
T4 468326 0 0 0
T5 165764 0 0 0
T6 103 0 0 0
T10 3475 2147 0 0
T11 4780 3292 0 0
T12 0 718 0 0
T25 2298 0 0 0
T26 5631 4216 0 0
T27 0 4189 0 0
T28 0 4171 0 0
T32 788 0 0 0
T33 1055 0 0 0
T40 0 2077 0 0
T41 0 1325 0 0
T52 0 725 0 0

DepthKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239957160 239800202 0 0
T1 1396 1341 0 0
T2 1157 1107 0 0
T3 3222 3131 0 0
T4 468326 468313 0 0
T10 3475 3388 0 0
T11 4780 4690 0 0
T25 2298 2212 0 0
T26 5631 5572 0 0
T32 788 688 0 0
T33 1055 971 0 0

RvalidKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239957160 239800202 0 0
T1 1396 1341 0 0
T2 1157 1107 0 0
T3 3222 3131 0 0
T4 468326 468313 0 0
T10 3475 3388 0 0
T11 4780 4690 0 0
T25 2298 2212 0 0
T26 5631 5572 0 0
T32 788 688 0 0
T33 1055 971 0 0

WreadyKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 239957160 239800202 0 0
T1 1396 1341 0 0
T2 1157 1107 0 0
T3 3222 3131 0 0
T4 468326 468313 0 0
T10 3475 3388 0 0
T11 4780 4690 0 0
T25 2298 2212 0 0
T26 5631 5572 0 0
T32 788 688 0 0
T33 1055 971 0 0

gen_normal_fifo.depthShallNotExceedParamDepth
NameAttemptsReal SuccessesFailuresIncomplete
Total 239957160 550217 0 0
T3 3222 1274 0 0
T4 468326 0 0 0
T5 165764 0 0 0
T6 1551 109 0 0
T10 3475 2147 0 0
T11 4780 3292 0 0
T15 0 1144 0 0
T23 0 167 0 0
T25 2298 0 0 0
T26 5631 4216 0 0
T27 0 4189 0 0
T28 0 4171 0 0
T32 788 0 0 0
T33 1055 0 0 0
T52 0 725 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%