Unified Coverage Report :: Module :: prim_count

Module : prim_count

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.29			71.29

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_count_0/rtl/prim_count.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_count_max_reqs_cntr	71.29			71.29

---

Module Instance : tb.dut.u_edn_core.u_prim_count_max_reqs_cntr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.29			71.29

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
71.29			71.29

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : prim_count

	Total	Covered	Percent
Totals	8	7	87.50
Total Bits	202	144	71.29
Total Bits 0->1	101	74	73.27
Total Bits 1->0	101	70	69.31

Ports	8	7	87.50
Port Bits	202	144	71.29
Port Bits 0->1	101	74	73.27
Port Bits 1->0	101	70	69.31

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clr_i	Unreachable	Unreachable		Unreachable		INPUT
set_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
set_cnt_i[0]	Yes	Yes	*T7,*T8,*T9	Yes	T3,T10,T11	INPUT
set_cnt_i[4:1]	No	No		Yes	T12,T13,T14	INPUT
set_cnt_i[31:5]	No	No		No		INPUT
incr_en_i	Unreachable	Unreachable		Unreachable		INPUT
decr_en_i	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	INPUT
step_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
commit_i	Unreachable	Unreachable		Unreachable		INPUT
cnt_o[31:0]	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	OUTPUT
cnt_after_commit_o[31:0]	Yes	Yes	T3,T10,T11	Yes	T3,T10,T11	OUTPUT
err_o	Yes	Yes	T15,T16,T17	Yes	T15,T16,T17	OUTPUT

*Tests covering at least one bit in the range