Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.59 83.33 100.00 67.44

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 83.59 83.33 100.00 67.44



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
83.59 83.33 100.00 67.44


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.10 98.27 93.44 96.79 82.66 96.87 96.58


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 90.61 99.92 91.87 70.79 82.66 99.55 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.95 95.02 97.57 100.00 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT3,T12,T13

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT14,T15,T16
10CoveredT1,T2,T4

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1168 1168 100.00
Total Bits 0->1 584 584 100.00
Total Bits 1->0 584 584 100.00

Ports 69 69 100.00
Port Bits 1168 1168 100.00
Port Bits 0->1 584 584 100.00
Port Bits 1->0 584 584 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T1,T2,T4 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T3,T17,T18 Yes T3,T17,T18 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T2,T3,T17 Yes T2,T3,T17 INPUT
tl_i.a_source[7:0] Yes Yes T2,T3,T17 Yes T2,T3,T17 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T19,T20,T21 Yes T19,T20,T21 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T3,T17,T8 Yes T3,T17,T8 INPUT
edn_i[1].edn_req Yes Yes T4,T22,T23 Yes T4,T22,T23 INPUT
edn_i[2].edn_req Yes Yes T22,T24,T25 Yes T22,T24,T25 INPUT
edn_i[3].edn_req Yes Yes T22,T12,T26 Yes T22,T12,T26 INPUT
edn_i[4].edn_req Yes Yes T2,T3,T22 Yes T2,T3,T22 INPUT
edn_i[5].edn_req Yes Yes T22,T13,T25 Yes T22,T13,T25 INPUT
edn_i[6].edn_req Yes Yes T1,T12,T27 Yes T1,T12,T27 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T3,T8,T28 Yes T3,T17,T8 OUTPUT
edn_o[0].edn_fips Yes Yes T8,T29,T30 Yes T3,T17,T8 OUTPUT
edn_o[0].edn_ack Yes Yes T3,T17,T8 Yes T3,T17,T8 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T22,T23,T31 Yes T22,T23,T31 OUTPUT
edn_o[1].edn_fips Yes Yes T4,T31,T32 Yes T4,T22,T23 OUTPUT
edn_o[1].edn_ack Yes Yes T4,T22,T23 Yes T4,T22,T23 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T22,T24,T25 Yes T22,T24,T25 OUTPUT
edn_o[2].edn_fips Yes Yes T22,T33,T34 Yes T22,T25,T33 OUTPUT
edn_o[2].edn_ack Yes Yes T22,T24,T25 Yes T22,T24,T25 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T22,T12,T26 Yes T22,T12,T26 OUTPUT
edn_o[3].edn_fips Yes Yes T22,T24,T6 Yes T22,T12,T24 OUTPUT
edn_o[3].edn_ack Yes Yes T22,T12,T26 Yes T22,T12,T26 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T3,T22,T35 Yes T3,T22,T35 OUTPUT
edn_o[4].edn_fips Yes Yes T3,T35,T6 Yes T3,T22,T35 OUTPUT
edn_o[4].edn_ack Yes Yes T3,T22,T35 Yes T3,T22,T35 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T22,T13,T25 Yes T22,T13,T25 OUTPUT
edn_o[5].edn_fips Yes Yes T36,T37,T38 Yes T22,T25,T39 OUTPUT
edn_o[5].edn_ack Yes Yes T22,T13,T25 Yes T22,T13,T25 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T12,T40,T25 Yes T12,T40,T25 OUTPUT
edn_o[6].edn_fips Yes Yes T40,T25,T33 Yes T40,T25,T33 OUTPUT
edn_o[6].edn_ack Yes Yes T12,T40,T25 Yes T12,T40,T25 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T3,T17 Yes T1,T3,T17 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T8,T22,T12 Yes T8,T22,T29 INPUT
csrng_cmd_i.genbits_fips Yes Yes T8,T22,T29 Yes T8,T22,T12 INPUT
csrng_cmd_i.genbits_valid Yes Yes T3,T17,T4 Yes T3,T17,T4 INPUT
csrng_cmd_i.csrng_rsp_sts Yes Yes T3,T12,T13 Yes T3,T12,T13 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T3,T17 Yes T1,T3,T17 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T3,T12,T13 Yes T3,T12,T13 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T1,T2,T4 Yes T1,T2,T4 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T3,T12,T13 Yes T3,T12,T13 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T1,T2,T4 Yes T1,T2,T4 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T41,T42,T19 Yes T41,T42,T19 OUTPUT
intr_edn_fatal_err_o Yes Yes T35,T26,T41 Yes T35,T26,T41 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 43 43 100.00 29 67.44
Cover properties 0 0 0
Cover sequences 0 0 0
Total 43 43 100.00 29 67.44




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 181853414 181715616 0 0
CsrngAppIfOut_A 181853414 181715616 0 0
FpvSecCmCntAlertCheck_A 181853414 96 0 0
FpvSecCmMainFsmCheck_A 181853414 60 0 0
FpvSecCmRegWeOnehotCheck_A 181853414 60 0 0
IntrEdnCmdReqDoneKnownO_A 181853414 181715616 0 0
TlAReadyKnownO_A 181853414 181715616 0 0
TlDValidKnownO_A 181853414 181715616 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 181853414 60 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 181853414 60 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 181853414 60 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 181853414 60 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 181853414 60 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 181853414 60 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 181853414 60 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 181853414 0 0 0
gen_edn_if_asserts[0].EdnDataStable_A 181853414 0 0 0
gen_edn_if_asserts[0].EdnEndPointOut_A 181853414 181715616 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 181853414 126249 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 181853414 0 0 0
gen_edn_if_asserts[1].EdnDataStable_A 181853414 0 0 0
gen_edn_if_asserts[1].EdnEndPointOut_A 181853414 181715616 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 181853414 126249 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 181853414 0 0 0
gen_edn_if_asserts[2].EdnDataStable_A 181853414 0 0 0
gen_edn_if_asserts[2].EdnEndPointOut_A 181853414 181715616 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 181853414 126249 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 181853414 0 0 0
gen_edn_if_asserts[3].EdnDataStable_A 181853414 0 0 0
gen_edn_if_asserts[3].EdnEndPointOut_A 181853414 181715616 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 181853414 126249 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 181853414 0 0 0
gen_edn_if_asserts[4].EdnDataStable_A 181853414 0 0 0
gen_edn_if_asserts[4].EdnEndPointOut_A 181853414 181715616 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 181853414 126249 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 181853414 0 0 0
gen_edn_if_asserts[5].EdnDataStable_A 181853414 0 0 0
gen_edn_if_asserts[5].EdnEndPointOut_A 181853414 181715616 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 181853414 126249 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 181853414 0 0 0
gen_edn_if_asserts[6].EdnDataStable_A 181853414 0 0 0
gen_edn_if_asserts[6].EdnEndPointOut_A 181853414 181715616 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 181853414 126249 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 96 0 0
T7 3951 0 0 0
T9 1149 1 0 0
T10 0 1 0 0
T11 0 1 0 0
T19 319012 0 0 0
T36 737 0 0 0
T39 3603 0 0 0
T41 21248 0 0 0
T42 25149 0 0 0
T43 0 1 0 0
T44 0 1 0 0
T45 0 1 0 0
T46 0 1 0 0
T47 0 1 0 0
T48 0 1 0 0
T49 0 1 0 0
T50 3056 0 0 0
T51 1094 0 0 0
T52 1860 0 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 60 0 0
T14 17352 10 0 0
T15 0 10 0 0
T16 0 20 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1289 0 0 0
T56 341766 0 0 0
T57 2571 0 0 0
T58 1612 0 0 0
T59 12783 0 0 0
T60 2170 0 0 0
T61 1231 0 0 0
T62 567 0 0 0
T63 1269 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 60 0 0
T14 17352 10 0 0
T15 0 10 0 0
T16 0 20 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1289 0 0 0
T56 341766 0 0 0
T57 2571 0 0 0
T58 1612 0 0 0
T59 12783 0 0 0
T60 2170 0 0 0
T61 1231 0 0 0
T62 567 0 0 0
T63 1269 0 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 60 0 0
T14 17352 10 0 0
T15 0 10 0 0
T16 0 20 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1289 0 0 0
T56 341766 0 0 0
T57 2571 0 0 0
T58 1612 0 0 0
T59 12783 0 0 0
T60 2170 0 0 0
T61 1231 0 0 0
T62 567 0 0 0
T63 1269 0 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 60 0 0
T14 17352 10 0 0
T15 0 10 0 0
T16 0 20 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1289 0 0 0
T56 341766 0 0 0
T57 2571 0 0 0
T58 1612 0 0 0
T59 12783 0 0 0
T60 2170 0 0 0
T61 1231 0 0 0
T62 567 0 0 0
T63 1269 0 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 60 0 0
T14 17352 10 0 0
T15 0 10 0 0
T16 0 20 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1289 0 0 0
T56 341766 0 0 0
T57 2571 0 0 0
T58 1612 0 0 0
T59 12783 0 0 0
T60 2170 0 0 0
T61 1231 0 0 0
T62 567 0 0 0
T63 1269 0 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 60 0 0
T14 17352 10 0 0
T15 0 10 0 0
T16 0 20 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1289 0 0 0
T56 341766 0 0 0
T57 2571 0 0 0
T58 1612 0 0 0
T59 12783 0 0 0
T60 2170 0 0 0
T61 1231 0 0 0
T62 567 0 0 0
T63 1269 0 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 60 0 0
T14 17352 10 0 0
T15 0 10 0 0
T16 0 20 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1289 0 0 0
T56 341766 0 0 0
T57 2571 0 0 0
T58 1612 0 0 0
T59 12783 0 0 0
T60 2170 0 0 0
T61 1231 0 0 0
T62 567 0 0 0
T63 1269 0 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 60 0 0
T14 17352 10 0 0
T15 0 10 0 0
T16 0 20 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1289 0 0 0
T56 341766 0 0 0
T57 2571 0 0 0
T58 1612 0 0 0
T59 12783 0 0 0
T60 2170 0 0 0
T61 1231 0 0 0
T62 567 0 0 0
T63 1269 0 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 60 0 0
T14 17352 10 0 0
T15 0 10 0 0
T16 0 20 0 0
T53 0 10 0 0
T54 0 10 0 0
T55 1289 0 0 0
T56 341766 0 0 0
T57 2571 0 0 0
T58 1612 0 0 0
T59 12783 0 0 0
T60 2170 0 0 0
T61 1231 0 0 0
T62 567 0 0 0
T63 1269 0 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 126249 0 0
T1 887 352 0 0
T2 1558 630 0 0
T3 2413 0 0 0
T4 798 322 0 0
T8 6754 0 0 0
T9 0 650 0 0
T12 1961 0 0 0
T17 2689 0 0 0
T22 1643 0 0 0
T23 1406 0 0 0
T26 0 31 0 0
T27 0 362 0 0
T28 1647 0 0 0
T35 0 13 0 0
T64 0 912 0 0
T65 0 217 0 0
T66 0 352 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 126249 0 0
T1 887 352 0 0
T2 1558 630 0 0
T3 2413 0 0 0
T4 798 322 0 0
T8 6754 0 0 0
T9 0 650 0 0
T12 1961 0 0 0
T17 2689 0 0 0
T22 1643 0 0 0
T23 1406 0 0 0
T26 0 31 0 0
T27 0 362 0 0
T28 1647 0 0 0
T35 0 13 0 0
T64 0 912 0 0
T65 0 217 0 0
T66 0 352 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 126249 0 0
T1 887 352 0 0
T2 1558 630 0 0
T3 2413 0 0 0
T4 798 322 0 0
T8 6754 0 0 0
T9 0 650 0 0
T12 1961 0 0 0
T17 2689 0 0 0
T22 1643 0 0 0
T23 1406 0 0 0
T26 0 31 0 0
T27 0 362 0 0
T28 1647 0 0 0
T35 0 13 0 0
T64 0 912 0 0
T65 0 217 0 0
T66 0 352 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 126249 0 0
T1 887 352 0 0
T2 1558 630 0 0
T3 2413 0 0 0
T4 798 322 0 0
T8 6754 0 0 0
T9 0 650 0 0
T12 1961 0 0 0
T17 2689 0 0 0
T22 1643 0 0 0
T23 1406 0 0 0
T26 0 31 0 0
T27 0 362 0 0
T28 1647 0 0 0
T35 0 13 0 0
T64 0 912 0 0
T65 0 217 0 0
T66 0 352 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 126249 0 0
T1 887 352 0 0
T2 1558 630 0 0
T3 2413 0 0 0
T4 798 322 0 0
T8 6754 0 0 0
T9 0 650 0 0
T12 1961 0 0 0
T17 2689 0 0 0
T22 1643 0 0 0
T23 1406 0 0 0
T26 0 31 0 0
T27 0 362 0 0
T28 1647 0 0 0
T35 0 13 0 0
T64 0 912 0 0
T65 0 217 0 0
T66 0 352 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 126249 0 0
T1 887 352 0 0
T2 1558 630 0 0
T3 2413 0 0 0
T4 798 322 0 0
T8 6754 0 0 0
T9 0 650 0 0
T12 1961 0 0 0
T17 2689 0 0 0
T22 1643 0 0 0
T23 1406 0 0 0
T26 0 31 0 0
T27 0 362 0 0
T28 1647 0 0 0
T35 0 13 0 0
T64 0 912 0 0
T65 0 217 0 0
T66 0 352 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 0 0 0

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 181715616 0 0
T1 887 720 0 0
T2 1558 1405 0 0
T3 2413 2349 0 0
T4 798 627 0 0
T8 6754 6704 0 0
T12 1961 1884 0 0
T17 2689 2623 0 0
T22 1643 1590 0 0
T23 1406 1342 0 0
T28 1647 1552 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 181853414 126249 0 0
T1 887 352 0 0
T2 1558 630 0 0
T3 2413 0 0 0
T4 798 322 0 0
T8 6754 0 0 0
T9 0 650 0 0
T12 1961 0 0 0
T17 2689 0 0 0
T22 1643 0 0 0
T23 1406 0 0 0
T26 0 31 0 0
T27 0 362 0 0
T28 1647 0 0 0
T35 0 13 0 0
T64 0 912 0 0
T65 0 217 0 0
T66 0 352 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%