Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	182328183	8214486	0	0
boot_gen_cmd_rd_A	182328183	55995	0	0
boot_ins_cmd_rd_A	182328183	63720	0	0
ctrl_rd_A	182328183	55127	0	0
err_code_test_rd_A	182328183	63498	0	0
intr_enable_rd_A	182328183	64284	0	0
max_num_reqs_between_reseeds_rd_A	182328183	57354	0	0
regwen_rd_A	182328183	64482	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182328183	8214486	0	0
T10	923	0	0	0
T11	2976	0	0	0
T19	319012	180900	0	0
T20	0	100710	0	0
T21	0	354835	0	0
T37	2424	0	0	0
T93	2741	0	0	0
T125	353	0	0	0
T126	347	0	0	0
T140	2007	0	0	0
T141	0	84752	0	0
T183	1796	0	0	0
T190	5928	0	0	0
T193	0	108464	0	0
T194	0	217081	0	0
T195	0	149181	0	0
T196	0	158991	0	0
T197	0	173683	0	0
T198	0	121027	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182328183	55995	0	0
T76	2630	0	0	0
T141	250781	2647	0	0
T164	1820	0	0	0
T194	382582	0	0	0
T195	0	4377	0	0
T199	0	1733	0	0
T200	0	2166	0	0
T201	0	4387	0	0
T202	0	2856	0	0
T203	0	2049	0	0
T204	0	3759	0	0
T205	0	1277	0	0
T206	0	4070	0	0
T207	11784	0	0	0
T208	1531	0	0	0
T209	6218	0	0	0
T210	1603	0	0	0
T211	3050	0	0	0
T212	3043	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182328183	63720	0	0
T76	2630	0	0	0
T141	250781	2901	0	0
T164	1820	0	0	0
T194	382582	0	0	0
T195	0	5185	0	0
T199	0	1945	0	0
T200	0	2463	0	0
T201	0	4899	0	0
T202	0	3356	0	0
T203	0	2292	0	0
T204	0	4438	0	0
T205	0	1530	0	0
T206	0	4647	0	0
T207	11784	0	0	0
T208	1531	0	0	0
T209	6218	0	0	0
T210	1603	0	0	0
T211	3050	0	0	0
T212	3043	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182328183	55127	0	0
T5	2008	0	0	0
T24	3859	0	0	0
T25	3135	0	0	0
T26	1271	0	0	0
T33	5556	0	0	0
T34	1178	0	0	0
T40	6605	0	0	0
T65	468	0	0	0
T67	5416	7	0	0
T141	0	2609	0	0
T152	1027	0	0	0
T166	0	4	0	0
T195	0	4448	0	0
T199	0	1856	0	0
T200	0	2133	0	0
T201	0	4317	0	0
T208	0	3	0	0
T213	0	7	0	0
T214	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182328183	63498	0	0
T76	2630	0	0	0
T141	250781	2882	0	0
T164	1820	0	0	0
T194	382582	0	0	0
T195	0	5215	0	0
T199	0	2077	0	0
T200	0	2436	0	0
T201	0	4996	0	0
T202	0	3424	0	0
T203	0	2108	0	0
T204	0	4310	0	0
T205	0	1594	0	0
T206	0	4747	0	0
T207	11784	0	0	0
T208	1531	0	0	0
T209	6218	0	0	0
T210	1603	0	0	0
T211	3050	0	0	0
T212	3043	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182328183	64284	0	0
T76	2630	0	0	0
T141	250781	2910	0	0
T164	1820	0	0	0
T194	382582	0	0	0
T195	0	5216	0	0
T199	0	2021	0	0
T200	0	2376	0	0
T201	0	4514	0	0
T202	0	3187	0	0
T203	0	2507	0	0
T207	11784	0	0	0
T208	1531	0	0	0
T209	6218	0	0	0
T210	1603	0	0	0
T211	3050	0	0	0
T212	3043	0	0	0
T215	0	27	0	0
T216	0	37	0	0
T217	0	94	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182328183	57354	0	0
T76	2630	0	0	0
T141	250781	2667	0	0
T164	1820	0	0	0
T194	382582	0	0	0
T195	0	4612	0	0
T199	0	1835	0	0
T200	0	2129	0	0
T201	0	4446	0	0
T202	0	2917	0	0
T203	0	2008	0	0
T204	0	3906	0	0
T205	0	1358	0	0
T206	0	3823	0	0
T207	11784	0	0	0
T208	1531	0	0	0
T209	6218	0	0	0
T210	1603	0	0	0
T211	3050	0	0	0
T212	3043	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	182328183	64482	0	0
T76	2630	0	0	0
T141	250781	2894	0	0
T164	1820	0	0	0
T194	382582	0	0	0
T195	0	5129	0	0
T199	0	1966	0	0
T200	0	2638	0	0
T201	0	4801	0	0
T202	0	3092	0	0
T203	0	2312	0	0
T204	0	4565	0	0
T205	0	1372	0	0
T206	0	4428	0	0
T207	11784	0	0	0
T208	1531	0	0	0
T209	6218	0	0	0
T210	1603	0	0	0
T211	3050	0	0	0
T212	3043	0	0	0