Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	645933	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5315096

1

T1

43

T2

194

T3

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1569393	1			T1	94		T2	350		T3	28
values[0x0]	2029305	1			T1	18		T2	98		T3	4
values[0x1]	2362331	1			T1	23		T2	94		T3	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	316330	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

5644699

1

T1

75

T2

291

T3

17

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	23353	1			T25	465		T40	1		T26	453
valid_sources[0x01]	24104	1			T29	1		T9	1		T25	521
valid_sources[0x02]	23489	1			T28	1		T139	1		T25	478
valid_sources[0x03]	23593	1			T28	2		T5	2		T29	1
valid_sources[0x04]	22637	1			T30	2		T42	4		T52	11
valid_sources[0x05]	23539	1			T30	1		T28	1		T9	1
valid_sources[0x06]	26292	1			T30	1		T25	461		T17	2
valid_sources[0x07]	23828	1			T52	2		T25	466		T18	1
valid_sources[0x08]	24708	1			T28	1		T29	1		T25	494
valid_sources[0x09]	21735	1			T2	6		T28	1		T31	1
valid_sources[0x0a]	22513	1			T30	1		T29	2		T25	452
valid_sources[0x0b]	24435	1			T45	2		T5	1		T25	436
valid_sources[0x0c]	23389	1			T28	1		T25	458		T18	1
valid_sources[0x0d]	24828	1			T45	1		T28	4		T9	1
valid_sources[0x0e]	22578	1			T23	10		T28	1		T29	2
valid_sources[0x0f]	23010	1			T3	1		T23	3		T25	420
valid_sources[0x10]	24214	1			T30	1		T43	1		T28	1
valid_sources[0x11]	22801	1			T30	1		T28	1		T9	1
valid_sources[0x12]	24292	1			T3	2		T25	485		T10	1
valid_sources[0x13]	23509	1			T30	2		T28	1		T31	1
valid_sources[0x14]	23306	1			T28	7		T5	2		T31	2
valid_sources[0x15]	24111	1			T28	1		T25	450		T11	2
valid_sources[0x16]	23167	1			T29	1		T25	448		T26	426
valid_sources[0x17]	22146	1			T2	57		T28	1		T5	2
valid_sources[0x18]	22783	1			T30	2		T28	2		T29	1
valid_sources[0x19]	21420	1			T28	1		T31	1		T29	2
valid_sources[0x1a]	23335	1			T2	24		T30	1		T28	1
valid_sources[0x1b]	21354	1			T45	1		T30	1		T25	418
valid_sources[0x1c]	25364	1			T3	1		T45	1		T9	2
valid_sources[0x1d]	23703	1			T5	1		T25	464		T17	1
valid_sources[0x1e]	24465	1			T30	2		T9	2		T25	439
valid_sources[0x1f]	22899	1			T45	2		T30	1		T28	3
valid_sources[0x20]	21692	1			T23	8		T52	5		T28	1
valid_sources[0x21]	23282	1			T2	10		T30	1		T9	1
valid_sources[0x22]	22532	1			T2	1		T5	1		T29	3
valid_sources[0x23]	22513	1			T30	5		T28	1		T29	1
valid_sources[0x24]	23228	1			T31	2		T29	2		T25	416
valid_sources[0x25]	24694	1			T28	1		T5	1		T29	5
valid_sources[0x26]	24700	1			T45	2		T28	1		T31	3
valid_sources[0x27]	22948	1			T2	9		T45	1		T30	1
valid_sources[0x28]	24229	1			T23	5		T31	1		T29	1
valid_sources[0x29]	23624	1			T28	1		T5	1		T31	1
valid_sources[0x2a]	23871	1			T30	1		T43	1		T52	8
valid_sources[0x2b]	22384	1			T45	2		T30	2		T28	3
valid_sources[0x2c]	21527	1			T30	2		T5	1		T9	2
valid_sources[0x2d]	22381	1			T2	3		T29	1		T9	1
valid_sources[0x2e]	24428	1			T28	3		T31	1		T25	472
valid_sources[0x2f]	23694	1			T23	10		T28	3		T25	451
valid_sources[0x30]	23150	1			T45	1		T52	6		T28	1
valid_sources[0x31]	22909	1			T28	3		T9	1		T25	453
valid_sources[0x32]	23647	1			T28	1		T25	467		T17	1
valid_sources[0x33]	23762	1			T28	2		T25	456		T40	2
valid_sources[0x34]	21950	1			T29	2		T25	447		T18	1
valid_sources[0x35]	23991	1			T28	1		T25	483		T18	1
valid_sources[0x36]	23620	1			T52	1		T5	2		T29	1
valid_sources[0x37]	24064	1			T3	4		T5	1		T31	1
valid_sources[0x38]	24539	1			T30	1		T31	3		T29	1
valid_sources[0x39]	22756	1			T30	1		T28	4		T25	519
valid_sources[0x3a]	24675	1			T3	1		T4	18		T25	467
valid_sources[0x3b]	23398	1			T30	3		T28	2		T31	1
valid_sources[0x3c]	23484	1			T2	18		T5	1		T25	455
valid_sources[0x3d]	23630	1			T30	2		T28	1		T31	1
valid_sources[0x3e]	23605	1			T23	2		T28	1		T5	1
valid_sources[0x3f]	23836	1			T2	10		T29	1		T9	3
valid_sources[0x40]	23705	1			T23	1		T25	474		T10	1
valid_sources[0x41]	23592	1			T2	50		T3	1		T43	2
valid_sources[0x42]	22437	1			T31	1		T9	1		T25	454
valid_sources[0x43]	23108	1			T28	5		T5	3		T25	444
valid_sources[0x44]	22135	1			T45	1		T25	482		T12	1
valid_sources[0x45]	22534	1			T30	1		T28	2		T31	1
valid_sources[0x46]	24105	1			T24	73		T43	6		T28	2
valid_sources[0x47]	23087	1			T2	14		T31	1		T25	445
valid_sources[0x48]	23324	1			T31	1		T25	411		T11	2
valid_sources[0x49]	23504	1			T9	1		T25	506		T18	1
valid_sources[0x4a]	22703	1			T30	1		T28	1		T31	1
valid_sources[0x4b]	23220	1			T2	18		T3	1		T30	1
valid_sources[0x4c]	23652	1			T28	2		T31	1		T29	2
valid_sources[0x4d]	22911	1			T25	487		T15	15		T18	1
valid_sources[0x4e]	24570	1			T30	1		T25	461		T10	1
valid_sources[0x4f]	22400	1			T2	14		T28	2		T9	1
valid_sources[0x50]	23304	1			T28	1		T25	423		T12	3
valid_sources[0x51]	23662	1			T5	1		T25	503		T12	7
valid_sources[0x52]	23839	1			T30	1		T28	2		T9	1
valid_sources[0x53]	22225	1			T5	1		T31	1		T9	2
valid_sources[0x54]	22933	1			T52	6		T28	2		T9	1
valid_sources[0x55]	23674	1			T1	135		T28	1		T25	463
valid_sources[0x56]	22467	1			T42	2		T28	2		T5	1
valid_sources[0x57]	22251	1			T42	2		T25	424		T12	3
valid_sources[0x58]	22443	1			T30	1		T5	3		T31	1
valid_sources[0x59]	23616	1			T28	1		T31	2		T25	432
valid_sources[0x5a]	24295	1			T42	1		T28	3		T25	473
valid_sources[0x5b]	23658	1			T25	498		T12	2		T26	476
valid_sources[0x5c]	23302	1			T30	2		T52	11		T44	41
valid_sources[0x5d]	24525	1			T2	9		T45	1		T30	1
valid_sources[0x5e]	23660	1			T28	2		T29	1		T25	430
valid_sources[0x5f]	23292	1			T31	2		T9	2		T139	11
valid_sources[0x60]	23780	1			T5	1		T25	452		T26	457
valid_sources[0x61]	24079	1			T23	2		T30	1		T28	2
valid_sources[0x62]	21922	1			T28	2		T29	1		T9	1
valid_sources[0x63]	22647	1			T30	1		T28	2		T9	2
valid_sources[0x64]	23479	1			T2	1		T30	3		T43	5
valid_sources[0x65]	23820	1			T28	1		T139	5		T25	467
valid_sources[0x66]	24460	1			T28	4		T139	4		T25	447
valid_sources[0x67]	22655	1			T5	1		T29	1		T25	479
valid_sources[0x68]	22228	1			T30	1		T28	1		T29	1
valid_sources[0x69]	23754	1			T31	1		T25	410		T40	1
valid_sources[0x6a]	23833	1			T28	1		T5	1		T31	2
valid_sources[0x6b]	21589	1			T2	24		T28	1		T31	1
valid_sources[0x6c]	24278	1			T5	1		T31	1		T29	2
valid_sources[0x6d]	24126	1			T30	2		T43	1		T28	1
valid_sources[0x6e]	24364	1			T25	428		T18	1		T26	380
valid_sources[0x6f]	23194	1			T30	2		T28	1		T5	1
valid_sources[0x70]	23691	1			T30	1		T28	1		T31	1
valid_sources[0x71]	22127	1			T28	4		T31	1		T9	1
valid_sources[0x72]	24419	1			T2	10		T30	1		T28	1
valid_sources[0x73]	23490	1			T2	14		T30	1		T52	7
valid_sources[0x74]	22724	1			T30	3		T28	1		T31	2
valid_sources[0x75]	24168	1			T30	1		T28	2		T31	2
valid_sources[0x76]	23725	1			T30	2		T31	2		T29	1
valid_sources[0x77]	23486	1			T52	2		T25	465		T10	1
valid_sources[0x78]	23575	1			T52	5		T5	1		T31	1
valid_sources[0x79]	23725	1			T45	1		T30	1		T9	1
valid_sources[0x7a]	22858	1			T31	3		T25	456		T17	1
valid_sources[0x7b]	24694	1			T139	1		T25	452		T26	424
valid_sources[0x7c]	22277	1			T28	2		T25	470		T26	432
valid_sources[0x7d]	24725	1			T2	16		T28	2		T5	1
valid_sources[0x7e]	23253	1			T30	1		T5	1		T9	2
valid_sources[0x7f]	23653	1			T29	1		T25	492		T26	393
valid_sources[0x80]	23400	1			T25	465		T40	1		T26	449

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1339298

1

T1

5

T2

87

T3

4

values[0x0]

all_enables

biggest_size

1988575

1

T1

16

T2

66

T3

2

values[0x1]

all_enables

biggest_size

1987223

1

T1

22

T2

41

T3

2