Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
67.19	67.19	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	67.19	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
67.19	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	21	31	59.62

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	21	31	59.62	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2476	1			T1	1		T2	3		T34	1
non_zero_bins[1]	1720	1			T1	2		T2	2		T23	1
zero	7857	1			T1	4		T2	25		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	455	1			T2	2		T34	1		T31	1
uni	3304	1			T1	2		T2	9		T3	1
gen	3700	1			T1	2		T2	9		T3	1
res	785	1			T1	1		T2	1		T24	1
ins	3809	1			T1	2		T2	9		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8059

1

T1

5

T2

22

T3

2

mubi_true

3994

1

T1

2

T2

8

T3

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T11

1

T17

1

T18

1

pass

12003

1

T1

7

T2

30

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	21	31	59.62	21
Automatically Generated Cross Bins	52	21	31	59.62	21
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	8
[ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	4

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res]	[zero]	[fail]	[mubi_true]	--	--	2

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	108	1			T25	3		T26	5		T149	1
upd	non_zero_bins[0]	pass	mubi_true	107	1			T2	1		T25	4		T26	5
upd	non_zero_bins[1]	pass	mubi_false	69	1			T2	1		T25	1		T26	1
upd	non_zero_bins[1]	pass	mubi_true	80	1			T31	1		T25	2		T26	5
upd	zero	pass	mubi_false	49	1			T34	1		T25	2		T26	3
upd	zero	pass	mubi_true	42	1			T25	3		T148	1		T187	1
uni	zero	fail	mubi_false	10	1			T126	1		T127	1		T128	1
uni	zero	pass	mubi_false	2404	1			T1	2		T2	5		T34	2
uni	zero	pass	mubi_true	890	1			T2	4		T3	1		T23	1
gen	non_zero_bins[0]	pass	mubi_false	470	1			T2	2		T25	13		T26	14
gen	non_zero_bins[0]	pass	mubi_true	522	1			T24	1		T52	1		T29	1
gen	non_zero_bins[1]	pass	mubi_false	291	1			T1	1		T25	7		T26	7
gen	non_zero_bins[1]	pass	mubi_true	320	1			T23	1		T31	1		T25	5
gen	zero	fail	mubi_false	23	1			T17	1		T41	1		T153	1
gen	zero	pass	mubi_false	1677	1			T1	1		T2	6		T3	1
gen	zero	pass	mubi_true	397	1			T2	1		T34	1		T4	2
res	non_zero_bins[0]	pass	mubi_false	150	1			T25	1		T38	1		T26	1
res	non_zero_bins[0]	pass	mubi_true	196	1			T24	1		T25	2		T140	1
res	non_zero_bins[1]	pass	mubi_false	137	1			T1	1		T29	1		T25	1
res	non_zero_bins[1]	pass	mubi_true	128	1			T52	1		T9	2		T25	2
res	zero	fail	mubi_false	8	1			T11	1		T18	1		T152	1
res	zero	pass	mubi_false	92	1			T25	2		T67	2		T148	1
res	zero	pass	mubi_true	74	1			T2	1		T25	3		T10	4
ins	non_zero_bins[0]	pass	mubi_false	489	1			T30	1		T25	13		T26	15
ins	non_zero_bins[0]	pass	mubi_true	434	1			T1	1		T34	1		T23	1
ins	non_zero_bins[1]	pass	mubi_false	330	1			T52	1		T25	7		T26	8
ins	non_zero_bins[1]	pass	mubi_true	365	1			T2	1		T24	1		T9	1
ins	zero	fail	mubi_false	5	1			T109	1		T155	1		T229	1
ins	zero	fail	mubi_true	4	1			T108	1		T110	1		T230	1
ins	zero	pass	mubi_false	1747	1			T2	8		T3	1		T4	1
ins	zero	pass	mubi_true	435	1			T1	1		T34	1		T4	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded