Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	588945	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

4670822

1

T1

29

T2

2

T3

10

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1399607	1			T1	48		T2	1		T3	27
values[0x0]	1786181	1			T1	14		T3	7		T7	16
values[0x1]	2073979	1			T1	17		T2	3		T3	1

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	294007	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

4965760

1

T1

50

T2

3

T3

16

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	19041	1			T1	1		T24	1		T10	6
valid_sources[0x01]	20424	1			T1	1		T7	1		T11	3
valid_sources[0x02]	18647	1			T1	2		T11	1		T6	11
valid_sources[0x03]	19603	1			T10	3		T11	2		T25	151
valid_sources[0x04]	20815	1			T1	1		T10	1		T11	8
valid_sources[0x05]	18973	1			T1	3		T7	1		T10	1
valid_sources[0x06]	19223	1			T1	1		T15	4		T8	1
valid_sources[0x07]	20096	1			T7	3		T15	2		T16	1
valid_sources[0x08]	21607	1			T1	1		T11	1		T15	4
valid_sources[0x09]	21339	1			T1	1		T3	1		T7	1
valid_sources[0x0a]	20069	1			T7	1		T28	1		T16	4
valid_sources[0x0b]	20589	1			T1	1		T7	1		T24	1
valid_sources[0x0c]	19552	1			T7	1		T28	1		T15	2
valid_sources[0x0d]	19803	1			T1	1		T11	3		T15	2
valid_sources[0x0e]	19617	1			T7	2		T10	2		T15	1
valid_sources[0x0f]	20018	1			T15	2		T25	87		T53	2
valid_sources[0x10]	19925	1			T3	1		T11	2		T25	110
valid_sources[0x11]	19722	1			T15	1		T25	100		T52	5
valid_sources[0x12]	20696	1			T1	1		T7	1		T24	1
valid_sources[0x13]	19115	1			T7	3		T24	1		T6	13
valid_sources[0x14]	21687	1			T11	1		T28	2		T15	1
valid_sources[0x15]	19692	1			T7	2		T11	1		T15	1
valid_sources[0x16]	20476	1			T7	3		T24	3		T15	1
valid_sources[0x17]	21174	1			T24	1		T11	2		T28	1
valid_sources[0x18]	19490	1			T7	2		T24	2		T15	1
valid_sources[0x19]	20248	1			T3	1		T11	2		T28	2
valid_sources[0x1a]	21214	1			T1	1		T15	1		T16	1
valid_sources[0x1b]	21152	1			T24	1		T11	1		T28	3
valid_sources[0x1c]	19969	1			T11	5		T28	1		T15	1
valid_sources[0x1d]	19399	1			T5	1		T28	1		T15	3
valid_sources[0x1e]	19814	1			T28	1		T15	2		T8	4
valid_sources[0x1f]	23659	1			T24	1		T15	3		T38	1
valid_sources[0x20]	19880	1			T11	3		T15	2		T25	56
valid_sources[0x21]	20348	1			T24	1		T15	4		T8	2
valid_sources[0x22]	20473	1			T1	1		T24	2		T4	1
valid_sources[0x23]	19922	1			T1	1		T10	3		T15	1
valid_sources[0x24]	21715	1			T1	2		T10	4		T6	4
valid_sources[0x25]	20877	1			T7	4		T10	2		T11	1
valid_sources[0x26]	19959	1			T11	1		T28	1		T15	4
valid_sources[0x27]	20278	1			T11	4		T6	2		T38	1
valid_sources[0x28]	20227	1			T24	1		T10	1		T11	2
valid_sources[0x29]	20014	1			T16	3		T25	58		T52	2
valid_sources[0x2a]	21592	1			T1	1		T24	1		T10	1
valid_sources[0x2b]	20239	1			T7	1		T11	1		T15	1
valid_sources[0x2c]	20999	1			T11	1		T28	2		T15	2
valid_sources[0x2d]	20839	1			T7	4		T11	2		T6	12
valid_sources[0x2e]	21625	1			T4	1		T10	3		T11	2
valid_sources[0x2f]	24020	1			T7	3		T24	1		T10	2
valid_sources[0x30]	21494	1			T15	3		T16	1		T25	155
valid_sources[0x31]	20053	1			T1	1		T7	4		T5	1
valid_sources[0x32]	20432	1			T15	3		T16	4		T42	1
valid_sources[0x33]	21954	1			T7	1		T24	1		T11	1
valid_sources[0x34]	19697	1			T24	1		T10	3		T11	1
valid_sources[0x35]	19417	1			T10	3		T15	1		T25	115
valid_sources[0x36]	21163	1			T1	1		T7	2		T24	1
valid_sources[0x37]	19644	1			T28	1		T15	2		T8	1
valid_sources[0x38]	20545	1			T10	1		T25	81		T26	692
valid_sources[0x39]	21092	1			T7	2		T24	3		T28	1
valid_sources[0x3a]	21935	1			T25	127		T53	1		T26	665
valid_sources[0x3b]	20913	1			T6	4		T28	2		T8	3
valid_sources[0x3c]	20316	1			T24	2		T28	1		T15	1
valid_sources[0x3d]	21962	1			T7	1		T28	1		T15	1
valid_sources[0x3e]	19566	1			T7	3		T11	1		T15	2
valid_sources[0x3f]	21230	1			T7	2		T11	1		T28	1
valid_sources[0x40]	20423	1			T24	1		T11	1		T15	2
valid_sources[0x41]	20239	1			T7	1		T11	2		T25	108
valid_sources[0x42]	20852	1			T1	1		T7	2		T10	3
valid_sources[0x43]	20091	1			T7	1		T24	2		T10	1
valid_sources[0x44]	19486	1			T10	1		T11	1		T15	1
valid_sources[0x45]	19737	1			T1	1		T7	4		T11	2
valid_sources[0x46]	19769	1			T1	1		T7	4		T15	2
valid_sources[0x47]	21062	1			T1	1		T7	3		T24	1
valid_sources[0x48]	19104	1			T1	1		T7	3		T24	2
valid_sources[0x49]	20151	1			T1	1		T10	1		T11	1
valid_sources[0x4a]	20863	1			T24	1		T15	4		T16	1
valid_sources[0x4b]	20213	1			T10	1		T11	2		T38	1
valid_sources[0x4c]	20545	1			T10	1		T11	1		T28	2
valid_sources[0x4d]	21214	1			T3	1		T7	1		T4	1
valid_sources[0x4e]	19744	1			T7	3		T24	3		T25	63
valid_sources[0x4f]	19630	1			T1	1		T7	3		T11	1
valid_sources[0x50]	20762	1			T24	1		T15	1		T16	1
valid_sources[0x51]	21024	1			T3	1		T7	3		T24	2
valid_sources[0x52]	19647	1			T1	1		T7	1		T24	1
valid_sources[0x53]	21384	1			T7	1		T11	1		T15	1
valid_sources[0x54]	22130	1			T10	2		T11	3		T28	2
valid_sources[0x55]	22491	1			T24	1		T10	2		T11	2
valid_sources[0x56]	18870	1			T24	3		T10	4		T28	1
valid_sources[0x57]	20076	1			T7	1		T4	1		T15	1
valid_sources[0x58]	21356	1			T7	1		T10	1		T28	1
valid_sources[0x59]	19164	1			T10	6		T15	2		T16	1
valid_sources[0x5a]	21876	1			T1	1		T11	1		T15	2
valid_sources[0x5b]	19927	1			T7	3		T28	1		T15	1
valid_sources[0x5c]	19735	1			T7	2		T24	2		T11	1
valid_sources[0x5d]	21195	1			T1	2		T11	1		T15	3
valid_sources[0x5e]	19893	1			T7	6		T24	1		T10	4
valid_sources[0x5f]	19807	1			T3	1		T7	7		T24	1
valid_sources[0x60]	20404	1			T7	1		T4	1		T6	3
valid_sources[0x61]	21216	1			T2	4		T11	2		T15	4
valid_sources[0x62]	23318	1			T10	5		T25	124		T52	2
valid_sources[0x63]	20416	1			T1	2		T24	1		T28	1
valid_sources[0x64]	19551	1			T4	1		T10	1		T38	3
valid_sources[0x65]	20721	1			T4	1		T11	2		T15	1
valid_sources[0x66]	20164	1			T1	1		T7	4		T10	1
valid_sources[0x67]	20819	1			T3	1		T24	1		T28	1
valid_sources[0x68]	21065	1			T1	1		T7	1		T24	2
valid_sources[0x69]	19275	1			T1	1		T7	3		T23	28
valid_sources[0x6a]	20003	1			T1	1		T7	2		T16	1
valid_sources[0x6b]	20594	1			T10	3		T11	1		T5	4
valid_sources[0x6c]	21222	1			T1	1		T7	2		T38	1
valid_sources[0x6d]	20068	1			T15	3		T42	1		T38	1
valid_sources[0x6e]	20870	1			T10	1		T15	4		T25	149
valid_sources[0x6f]	20105	1			T7	3		T10	2		T15	1
valid_sources[0x70]	19832	1			T7	2		T16	1		T38	1
valid_sources[0x71]	20146	1			T1	1		T11	2		T28	1
valid_sources[0x72]	19255	1			T3	1		T10	1		T15	2
valid_sources[0x73]	20966	1			T7	1		T10	1		T11	3
valid_sources[0x74]	21810	1			T11	2		T59	38		T15	5
valid_sources[0x75]	21387	1			T7	1		T24	1		T11	7
valid_sources[0x76]	21148	1			T7	1		T24	1		T10	1
valid_sources[0x77]	21821	1			T3	1		T7	3		T24	3
valid_sources[0x78]	20445	1			T7	3		T11	2		T25	76
valid_sources[0x79]	20342	1			T1	1		T7	1		T24	1
valid_sources[0x7a]	20102	1			T1	1		T3	1		T25	92
valid_sources[0x7b]	19625	1			T7	3		T10	2		T11	1
valid_sources[0x7c]	20447	1			T24	1		T15	1		T42	1
valid_sources[0x7d]	21317	1			T10	4		T16	1		T25	105
valid_sources[0x7e]	19897	1			T1	1		T15	1		T38	3
valid_sources[0x7f]	20843	1			T1	1		T7	1		T24	2
valid_sources[0x80]	21859	1			T7	1		T4	1		T11	1

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1176947

1

T1

2

T3

5

T7

7

values[0x0]

all_enables

biggest_size

1748784

1

T1

12

T3

4

T7

15

values[0x1]

all_enables

biggest_size

1745091

1

T1

15

T2

2

T3

1