Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2377	1			T1	2		T10	1		T11	1
non_zero_bins[1]	1774	1			T1	1		T7	1		T24	1
zero	8203	1			T1	2		T2	2		T3	3

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	498	1			T28	1		T25	6		T53	1
uni	3468	1			T1	2		T3	1		T7	1
gen	3693	1			T1	1		T2	1		T3	1
res	733	1			T10	1		T11	2		T15	2
ins	3962	1			T1	2		T2	1		T3	1

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

8396

1

T1

1

T2

1

T3

3

mubi_true

3958

1

T1

4

T2

1

T7

1

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

50

1

T18

1

T19

1

T20

1

pass

12304

1

T1

5

T2

2

T3

3

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	109	1			T28	1		T26	3		T43	1
upd	non_zero_bins[0]	pass	mubi_true	107	1			T25	3		T26	4		T27	1
upd	non_zero_bins[1]	pass	mubi_false	83	1			T53	1		T26	1		T139	1
upd	non_zero_bins[1]	pass	mubi_true	87	1			T25	1		T26	3		T34	1
upd	zero	pass	mubi_false	56	1			T25	1		T26	1		T234	1
upd	zero	pass	mubi_true	56	1			T25	1		T26	4		T137	1
uni	zero	fail	mubi_false	6	1			T19	1		T116	1		T117	1
uni	zero	pass	mubi_false	2496	1			T1	1		T3	1		T7	1
uni	zero	pass	mubi_true	966	1			T1	1		T59	1		T25	8
gen	non_zero_bins[0]	pass	mubi_false	416	1			T10	1		T28	1		T25	2
gen	non_zero_bins[0]	pass	mubi_true	437	1			T1	1		T25	4		T52	2
gen	non_zero_bins[1]	pass	mubi_false	338	1			T25	4		T53	1		T26	10
gen	non_zero_bins[1]	pass	mubi_true	305	1			T25	1		T26	3		T43	1
gen	zero	fail	mubi_false	26	1			T18	1		T95	1		T62	1
gen	zero	pass	mubi_false	1761	1			T3	1		T7	1		T11	2
gen	zero	pass	mubi_true	410	1			T2	1		T24	1		T32	1
res	non_zero_bins[0]	pass	mubi_false	174	1			T25	1		T54	2		T140	1
res	non_zero_bins[0]	pass	mubi_true	165	1			T38	1		T30	3		T27	2
res	non_zero_bins[1]	pass	mubi_false	124	1			T10	1		T11	2		T15	2
res	non_zero_bins[1]	pass	mubi_true	118	1			T25	1		T52	1		T29	2
res	zero	fail	mubi_false	9	1			T20	1		T147	1		T183	1
res	zero	pass	mubi_false	71	1			T25	1		T9	1		T72	2
res	zero	pass	mubi_true	72	1			T51	1		T52	1		T26	1
ins	non_zero_bins[0]	pass	mubi_false	493	1			T11	1		T38	1		T25	7
ins	non_zero_bins[0]	pass	mubi_true	476	1			T1	1		T28	1		T51	1
ins	non_zero_bins[1]	pass	mubi_false	327	1			T15	1		T25	2		T52	1
ins	non_zero_bins[1]	pass	mubi_true	392	1			T1	1		T7	1		T24	1
ins	zero	fail	mubi_false	9	1			T100	1		T101	1		T102	1
ins	zero	pass	mubi_false	1898	1			T2	1		T3	1		T7	1
ins	zero	pass	mubi_true	367	1			T24	1		T28	1		T18	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded