Module Definition
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Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.14 100.00 100.00 85.71 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.57 100.00 100.00 92.86 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.49 100.00 89.95 100.00 100.00 u_edn_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_state_regs 100.00 100.00 100.00 100.00

Line Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Module : edn_ack_sm
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT32,T6,T8

FSM Coverage for Module : edn_ack_sm
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T1,T3,T7
DataWait 75 Covered T1,T3,T7
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T6
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T113,T115,T153
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T3,T7
DataWait->AckPls 80 Covered T1,T3,T7
DataWait->Disabled 107 Covered T30,T66,T105
DataWait->Error 99 Covered T8,T103,T49
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T21,T22
EndPointClear->Disabled 107 Covered T32,T154,T144
EndPointClear->Error 99 Covered T16,T17,T61
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T3,T7
Idle->Disabled 107 Covered T6,T8,T16
Idle->Error 99 Covered T4,T5,T6



Branch Coverage for Module : edn_ack_sm
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T3,T7
Idle - 1 0 - Covered T1,T3,T7
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T3,T7
DataWait - - - 0 Covered T1,T3,T7
AckPls - - - - Covered T1,T3,T7
Error - - - - Covered T4,T5,T6
default - - - - Covered T16,T118,T90


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T32,T6,T8
0 0 Covered T1,T2,T3


Assert Coverage for Module : edn_ack_sm
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 1386993041 915284 0 0
FpvSecCmErrorStEscalate_A 1386993041 921206 0 0
u_state_regs_A 1386964406 1385898747 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1386993041 915284 0 0
T4 3297 1365 0 0
T5 12789 7791 0 0
T6 8491 4200 0 0
T8 0 2450 0 0
T9 0 8155 0 0
T10 43505 0 0 0
T11 45787 0 0 0
T15 62097 0 0 0
T16 0 33411 0 0
T17 0 7784 0 0
T23 9415 0 0 0
T28 15939 0 0 0
T31 0 7630 0 0
T32 7000 0 0 0
T57 0 8148 0 0
T59 8904 0 0 0
T61 0 7490 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1386993041 921206 0 0
T4 3297 1372 0 0
T5 12789 7798 0 0
T6 8491 4207 0 0
T8 0 2457 0 0
T9 0 8162 0 0
T10 43505 0 0 0
T11 45787 0 0 0
T15 62097 0 0 0
T16 0 34041 0 0
T17 0 7791 0 0
T23 9415 0 0 0
T28 15939 0 0 0
T31 0 7637 0 0
T32 7000 0 0 0
T57 0 8155 0 0
T59 8904 0 0 0
T61 0 7497 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1386964406 1385898747 0 0
T1 14854 14182 0 0
T2 5642 5236 0 0
T3 6993 6580 0 0
T4 3119 2069 0 0
T7 9772 9380 0 0
T10 43505 43001 0 0
T11 45787 45360 0 0
T23 9415 8764 0 0
T24 20300 19908 0 0
T32 7000 6622 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT32,T6,T8

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T28,T15,T29
DataWait 75 Covered T28,T15,T29
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T6
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T28,T15,T29
DataWait->AckPls 80 Covered T28,T15,T29
DataWait->Disabled 107 Covered T105,T155,T156
DataWait->Error 99 Covered T93,T99,T157
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T21,T22
EndPointClear->Disabled 107 Covered T32,T154,T144
EndPointClear->Error 99 Covered T16,T17,T61
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T28,T15,T29
Idle->Disabled 107 Covered T6,T8,T16
Idle->Error 99 Covered T4,T5,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T28,T15,T29
Idle - 1 0 - Covered T28,T15,T29
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T28,T15,T29
DataWait - - - 0 Covered T28,T15,T29
AckPls - - - - Covered T28,T15,T29
Error - - - - Covered T4,T5,T6
default - - - - Covered T16,T21,T22


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T32,T6,T8
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 198141863 131062 0 0
FpvSecCmErrorStEscalate_A 198141863 131908 0 0
u_state_regs_A 198141863 197989626 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131062 0 0
T4 471 195 0 0
T5 1827 1113 0 0
T6 1213 600 0 0
T8 0 350 0 0
T9 0 1165 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4773 0 0
T17 0 1112 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1090 0 0
T32 1000 0 0 0
T57 0 1164 0 0
T59 1272 0 0 0
T61 0 1070 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131908 0 0
T4 471 196 0 0
T5 1827 1114 0 0
T6 1213 601 0 0
T8 0 351 0 0
T9 0 1166 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4863 0 0
T17 0 1113 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1091 0 0
T32 1000 0 0 0
T57 0 1165 0 0
T59 1272 0 0 0
T61 0 1071 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 197989626 0 0
T1 2122 2026 0 0
T2 806 748 0 0
T3 999 940 0 0
T4 471 321 0 0
T7 1396 1340 0 0
T10 6215 6143 0 0
T11 6541 6480 0 0
T23 1345 1252 0 0
T24 2900 2844 0 0
T32 1000 946 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT32,T6,T8

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 12 85.71
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T15,T30,T29
DataWait 75 Covered T15,T30,T29
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T6
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Not Covered
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T15,T30,T29
DataWait->AckPls 80 Covered T15,T30,T29
DataWait->Disabled 107 Covered T30,T66,T78
DataWait->Error 99 Covered T103,T158,T159
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T21,T22
EndPointClear->Disabled 107 Covered T32,T154,T144
EndPointClear->Error 99 Covered T16,T17,T61
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T15,T30,T29
Idle->Disabled 107 Covered T6,T8,T16
Idle->Error 99 Covered T4,T5,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T15,T30,T29
Idle - 1 0 - Covered T15,T30,T31
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T15,T30,T29
DataWait - - - 0 Covered T15,T30,T29
AckPls - - - - Covered T15,T30,T29
Error - - - - Covered T4,T5,T6
default - - - - Covered T16,T21,T22


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T32,T6,T8
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 198141863 131062 0 0
FpvSecCmErrorStEscalate_A 198141863 131908 0 0
u_state_regs_A 198141863 197989626 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131062 0 0
T4 471 195 0 0
T5 1827 1113 0 0
T6 1213 600 0 0
T8 0 350 0 0
T9 0 1165 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4773 0 0
T17 0 1112 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1090 0 0
T32 1000 0 0 0
T57 0 1164 0 0
T59 1272 0 0 0
T61 0 1070 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131908 0 0
T4 471 196 0 0
T5 1827 1114 0 0
T6 1213 601 0 0
T8 0 351 0 0
T9 0 1166 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4863 0 0
T17 0 1113 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1091 0 0
T32 1000 0 0 0
T57 0 1165 0 0
T59 1272 0 0 0
T61 0 1071 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 197989626 0 0
T1 2122 2026 0 0
T2 806 748 0 0
T3 999 940 0 0
T4 471 321 0 0
T7 1396 1340 0 0
T10 6215 6143 0 0
T11 6541 6480 0 0
T23 1345 1252 0 0
T24 2900 2844 0 0
T32 1000 946 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT32,T6,T8

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T1,T3,T7
DataWait 75 Covered T1,T3,T7
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T6
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T160
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T1,T3,T7
DataWait->AckPls 80 Covered T1,T3,T7
DataWait->Disabled 107 Covered T67,T161
DataWait->Error 99 Covered T49,T50,T162
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T21,T22
EndPointClear->Disabled 107 Covered T32,T154,T144
EndPointClear->Error 99 Covered T16,T17,T61
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T1,T3,T7
Idle->Disabled 107 Covered T6,T8,T16
Idle->Error 99 Covered T4,T5,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T1,T3,T7
Idle - 1 0 - Covered T1,T3,T7
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T1,T3,T7
DataWait - - - 0 Covered T1,T3,T7
AckPls - - - - Covered T1,T3,T7
Error - - - - Covered T4,T5,T6
default - - - - Covered T16,T118,T90


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T32,T6,T8
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 198141863 128912 0 0
FpvSecCmErrorStEscalate_A 198141863 129758 0 0
u_state_regs_A 198113228 197960991 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 128912 0 0
T4 471 195 0 0
T5 1827 1113 0 0
T6 1213 600 0 0
T8 0 350 0 0
T9 0 1165 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4773 0 0
T17 0 1112 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1090 0 0
T32 1000 0 0 0
T57 0 1164 0 0
T59 1272 0 0 0
T61 0 1070 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 129758 0 0
T4 471 196 0 0
T5 1827 1114 0 0
T6 1213 601 0 0
T8 0 351 0 0
T9 0 1166 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4863 0 0
T17 0 1113 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1091 0 0
T32 1000 0 0 0
T57 0 1165 0 0
T59 1272 0 0 0
T61 0 1071 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198113228 197960991 0 0
T1 2122 2026 0 0
T2 806 748 0 0
T3 999 940 0 0
T4 293 143 0 0
T7 1396 1340 0 0
T10 6215 6143 0 0
T11 6541 6480 0 0
T23 1345 1252 0 0
T24 2900 2844 0 0
T32 1000 946 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT32,T6,T8

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T11,T15,T38
DataWait 75 Covered T11,T15,T8
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T6
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T163
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T11,T15,T38
DataWait->AckPls 80 Covered T11,T15,T38
DataWait->Disabled 107 Covered T164,T165,T166
DataWait->Error 99 Covered T8,T167,T111
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T21,T22
EndPointClear->Disabled 107 Covered T32,T154,T144
EndPointClear->Error 99 Covered T16,T17,T61
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T11,T15,T8
Idle->Disabled 107 Covered T6,T8,T16
Idle->Error 99 Covered T4,T5,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T11,T15,T38
Idle - 1 0 - Covered T11,T15,T8
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T11,T15,T38
DataWait - - - 0 Covered T11,T15,T8
AckPls - - - - Covered T11,T15,T38
Error - - - - Covered T4,T5,T6
default - - - - Covered T16,T21,T22


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T32,T6,T8
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 198141863 131062 0 0
FpvSecCmErrorStEscalate_A 198141863 131908 0 0
u_state_regs_A 198141863 197989626 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131062 0 0
T4 471 195 0 0
T5 1827 1113 0 0
T6 1213 600 0 0
T8 0 350 0 0
T9 0 1165 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4773 0 0
T17 0 1112 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1090 0 0
T32 1000 0 0 0
T57 0 1164 0 0
T59 1272 0 0 0
T61 0 1070 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131908 0 0
T4 471 196 0 0
T5 1827 1114 0 0
T6 1213 601 0 0
T8 0 351 0 0
T9 0 1166 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4863 0 0
T17 0 1113 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1091 0 0
T32 1000 0 0 0
T57 0 1165 0 0
T59 1272 0 0 0
T61 0 1071 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 197989626 0 0
T1 2122 2026 0 0
T2 806 748 0 0
T3 999 940 0 0
T4 471 321 0 0
T7 1396 1340 0 0
T10 6215 6143 0 0
T11 6541 6480 0 0
T23 1345 1252 0 0
T24 2900 2844 0 0
T32 1000 946 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT32,T6,T8

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T24,T15,T30
DataWait 75 Covered T24,T15,T30
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T6
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T115
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T24,T15,T30
DataWait->AckPls 80 Covered T24,T15,T30
DataWait->Disabled 107 Covered T168,T169,T170
DataWait->Error 99 Covered T85,T70,T171
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T21,T22
EndPointClear->Disabled 107 Covered T32,T154,T144
EndPointClear->Error 99 Covered T16,T17,T61
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T24,T15,T30
Idle->Disabled 107 Covered T6,T8,T16
Idle->Error 99 Covered T4,T5,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T24,T15,T30
Idle - 1 0 - Covered T24,T15,T30
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T24,T15,T30
DataWait - - - 0 Covered T24,T15,T30
AckPls - - - - Covered T24,T15,T30
Error - - - - Covered T4,T5,T6
default - - - - Covered T16,T21,T22


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T32,T6,T8
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 198141863 131062 0 0
FpvSecCmErrorStEscalate_A 198141863 131908 0 0
u_state_regs_A 198141863 197989626 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131062 0 0
T4 471 195 0 0
T5 1827 1113 0 0
T6 1213 600 0 0
T8 0 350 0 0
T9 0 1165 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4773 0 0
T17 0 1112 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1090 0 0
T32 1000 0 0 0
T57 0 1164 0 0
T59 1272 0 0 0
T61 0 1070 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131908 0 0
T4 471 196 0 0
T5 1827 1114 0 0
T6 1213 601 0 0
T8 0 351 0 0
T9 0 1166 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4863 0 0
T17 0 1113 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1091 0 0
T32 1000 0 0 0
T57 0 1165 0 0
T59 1272 0 0 0
T61 0 1071 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 197989626 0 0
T1 2122 2026 0 0
T2 806 748 0 0
T3 999 940 0 0
T4 471 321 0 0
T7 1396 1340 0 0
T10 6215 6143 0 0
T11 6541 6480 0 0
T23 1345 1252 0 0
T24 2900 2844 0 0
T32 1000 946 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT32,T6,T8

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T24,T10,T32
DataWait 75 Covered T24,T10,T32
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T6
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T172
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T24,T10,T32
DataWait->AckPls 80 Covered T24,T10,T32
DataWait->Disabled 107 Covered T60,T173,T174
DataWait->Error 99 Covered T5,T6,T104
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T21,T22
EndPointClear->Disabled 107 Covered T32,T154,T144
EndPointClear->Error 99 Covered T16,T17,T61
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T24,T10,T32
Idle->Disabled 107 Covered T6,T8,T16
Idle->Error 99 Covered T4,T8,T57



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T24,T10,T32
Idle - 1 0 - Covered T24,T10,T32
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T24,T10,T32
DataWait - - - 0 Covered T24,T10,T32
AckPls - - - - Covered T24,T10,T32
Error - - - - Covered T4,T5,T6
default - - - - Covered T16,T21,T22


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T32,T6,T8
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 198141863 131062 0 0
FpvSecCmErrorStEscalate_A 198141863 131908 0 0
u_state_regs_A 198141863 197989626 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131062 0 0
T4 471 195 0 0
T5 1827 1113 0 0
T6 1213 600 0 0
T8 0 350 0 0
T9 0 1165 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4773 0 0
T17 0 1112 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1090 0 0
T32 1000 0 0 0
T57 0 1164 0 0
T59 1272 0 0 0
T61 0 1070 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131908 0 0
T4 471 196 0 0
T5 1827 1114 0 0
T6 1213 601 0 0
T8 0 351 0 0
T9 0 1166 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4863 0 0
T17 0 1113 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1091 0 0
T32 1000 0 0 0
T57 0 1165 0 0
T59 1272 0 0 0
T61 0 1071 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 197989626 0 0
T1 2122 2026 0 0
T2 806 748 0 0
T3 999 940 0 0
T4 471 321 0 0
T7 1396 1340 0 0
T10 6215 6143 0 0
T11 6541 6480 0 0
T23 1345 1252 0 0
T24 2900 2844 0 0
T32 1000 946 0 0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
TOTAL3232100.00
ALWAYS5233100.00
ALWAYS552929100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
52 3 3
55 1 1
56 1 1
57 1 1
58 1 1
59 1 1
60 1 1
62 1 1
63 1 1
64 1 1
MISSING_ELSE
68 1 1
71 1 1
72 1 1
73 1 1
MISSING_ELSE
75 1 1
MISSING_ELSE
79 1 1
80 1 1
MISSING_ELSE
84 1 1
85 1 1
88 1 1
98 1 1
99 1 1
101 1 1
102 1 1
103 1 1
104 1 1
107 1 1
109 1 1
110 1 1
111 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalCoveredPercent
Conditions33100.00
Logical33100.00
Non-Logical00
Event00

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT32,T6,T8

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Summary for FSM :: state_q
TotalCoveredPercent
States 6 6 100.00 (Not included in score)
Transitions 14 13 92.86
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
AckPls 80 Covered T2,T28,T33
DataWait 75 Covered T2,T28,T33
Disabled 107 Covered T1,T2,T3
EndPointClear 63 Covered T1,T2,T3
Error 99 Covered T4,T5,T6
Idle 68 Covered T1,T2,T3


transitionsLine No.CoveredTests
AckPls->Disabled 107 Covered T113,T153,T175
AckPls->Error 99 Not Covered
AckPls->Idle 85 Covered T2,T28,T33
DataWait->AckPls 80 Covered T2,T28,T33
DataWait->Disabled 107 Covered T33,T106,T92
DataWait->Error 99 Covered T90,T47
Disabled->EndPointClear 63 Covered T1,T2,T3
Disabled->Error 99 Covered T16,T21,T22
EndPointClear->Disabled 107 Covered T32,T154,T144
EndPointClear->Error 99 Covered T16,T17,T61
EndPointClear->Idle 68 Covered T1,T2,T3
Idle->DataWait 75 Covered T2,T28,T33
Idle->Disabled 107 Covered T6,T8,T16
Idle->Error 99 Covered T4,T5,T6



Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
Line No.TotalCoveredPercent
Branches 16 16 100.00
IF 52 2 2 100.00
CASE 60 11 11 100.00
IF 98 3 3 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 52 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


LineNo. Expression -1-: 60 case (state_q) -2-: 62 if (enable_i) -3-: 71 if (req_i) -4-: 72 if (fifo_not_empty_i) -5-: 79 if (fifo_not_empty_i)

Branches:
-1--2--3--4--5-StatusTests
Disabled 1 - - - Covered T1,T2,T3
Disabled 0 - - - Covered T1,T2,T3
EndPointClear - - - - Covered T1,T2,T3
Idle - 1 1 - Covered T2,T28,T33
Idle - 1 0 - Covered T2,T28,T33
Idle - 0 - - Covered T1,T2,T3
DataWait - - - 1 Covered T2,T28,T33
DataWait - - - 0 Covered T2,T28,T33
AckPls - - - - Covered T2,T28,T33
Error - - - - Covered T4,T5,T6
default - - - - Covered T16,T21,T22


LineNo. Expression -1-: 98 if (local_escalate_i) -2-: 104 if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:
-1--2-StatusTests
1 - Covered T4,T5,T6
0 1 Covered T32,T6,T8
0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 3 3 100.00 3 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 3 3 100.00 3 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AckSmErrorStStable_A 198141863 131062 0 0
FpvSecCmErrorStEscalate_A 198141863 131908 0 0
u_state_regs_A 198141863 197989626 0 0


AckSmErrorStStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131062 0 0
T4 471 195 0 0
T5 1827 1113 0 0
T6 1213 600 0 0
T8 0 350 0 0
T9 0 1165 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4773 0 0
T17 0 1112 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1090 0 0
T32 1000 0 0 0
T57 0 1164 0 0
T59 1272 0 0 0
T61 0 1070 0 0

FpvSecCmErrorStEscalate_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 131908 0 0
T4 471 196 0 0
T5 1827 1114 0 0
T6 1213 601 0 0
T8 0 351 0 0
T9 0 1166 0 0
T10 6215 0 0 0
T11 6541 0 0 0
T15 8871 0 0 0
T16 0 4863 0 0
T17 0 1113 0 0
T23 1345 0 0 0
T28 2277 0 0 0
T31 0 1091 0 0
T32 1000 0 0 0
T57 0 1165 0 0
T59 1272 0 0 0
T61 0 1071 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 198141863 197989626 0 0
T1 2122 2026 0 0
T2 806 748 0 0
T3 999 940 0 0
T4 471 321 0 0
T7 1396 1340 0 0
T10 6215 6143 0 0
T11 6541 6480 0 0
T23 1345 1252 0 0
T24 2900 2844 0 0
T32 1000 946 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%