Unified Coverage Report :: Module :: edn_ack_sm

Module : edn_ack_sm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00
tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep	98.57	100.00	100.00		92.86	100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.14	100.00	100.00		85.71	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.57	100.00	100.00		92.86	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Module : edn_ack_sm

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T9

---

FSM Coverage for Module : edn_ack_sm

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T27
DataWait	75	Covered	T2,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T2,T3,T4
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T115,T149,T150
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T27
DataWait->AckPls	80	Covered	T2,T3,T27
DataWait->Disabled	107	Covered	T37,T58,T81
DataWait->Error	99	Covered	T4,T6,T53
Disabled->EndPointClear	63	Covered	T2,T3,T4
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T36,T109,T110
EndPointClear->Error	99	Covered	T20,T97,T151
EndPointClear->Idle	68	Covered	T2,T3,T4
Idle->DataWait	75	Covered	T2,T3,T4
Idle->Disabled	107	Covered	T2,T4,T17
Idle->Error	99	Covered	T4,T5,T23

---

Branch Coverage for Module : edn_ack_sm

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T4
Idle	-	1	1	-	Covered	T2,T3,T27
Idle	-	1	0	-	Covered	T2,T3,T4
Idle	-	0	-	-	Covered	T2,T3,T4
DataWait	-	-	-	1	Covered	T2,T3,T27
DataWait	-	-	-	0	Covered	T2,T3,T4
AckPls	-	-	-	-	Covered	T2,T3,T27
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T23,T20,T53

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T4,T17,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_ack_sm

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	1710292374	936154	0	0
FpvSecCmErrorStEscalate_A	1710292374	942104	0	0
u_state_regs_A	1710247849	1709179670	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1710292374	936154	0	0
T4	20447	7420	0	0
T5	6174	2688	0	0
T6	0	2450	0	0
T9	27013	0	0	0
T15	0	7504	0	0
T16	0	8106	0	0
T17	13027	0	0	0
T20	0	97104	0	0
T23	15225	7832	0	0
T24	6335252	0	0	0
T27	33551	0	0	0
T28	28098	0	0	0
T31	164087	0	0	0
T44	13699	0	0	0
T52	0	7987	0	0
T53	0	7776	0	0
T54	0	2695	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1710292374	942104	0	0
T4	20447	7427	0	0
T5	6174	2695	0	0
T6	0	2457	0	0
T9	27013	0	0	0
T15	0	7511	0	0
T16	0	8113	0	0
T17	13027	0	0	0
T20	0	98364	0	0
T23	15225	7839	0	0
T24	6335252	0	0	0
T27	33551	0	0	0
T28	28098	0	0	0
T31	164087	0	0	0
T44	13699	0	0	0
T52	0	7994	0	0
T53	0	7783	0	0
T54	0	2702	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1710247849	1709179670	0	0
T1	7602	7154	0	0
T2	71890	68509	0	0
T3	16457	15869	0	0
T4	19265	17921	0	0
T5	6032	5311	0	0
T9	27013	26481	0	0
T17	13027	12628	0	0
T23	15063	13880	0	0
T27	33551	33131	0	0
T28	28098	27727	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T2,T3,T27
DataWait	75	Covered	T2,T3,T4
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T2,T3,T4
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T2,T3,T27
DataWait->AckPls	80	Covered	T2,T3,T27
DataWait->Disabled	107	Covered	T152,T153
DataWait->Error	99	Covered	T4,T6,T154
Disabled->EndPointClear	63	Covered	T2,T3,T4
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T36,T109,T110
EndPointClear->Error	99	Covered	T20,T97,T151
EndPointClear->Idle	68	Covered	T2,T3,T4
Idle->DataWait	75	Covered	T2,T3,T4
Idle->Disabled	107	Covered	T2,T4,T17
Idle->Error	99	Covered	T5,T15,T16

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T4
Idle	-	1	1	-	Covered	T2,T3,T27
Idle	-	1	0	-	Covered	T2,T3,T4
Idle	-	0	-	-	Covered	T2,T3,T4
DataWait	-	-	-	1	Covered	T2,T3,T27
DataWait	-	-	-	0	Covered	T2,T3,T4
AckPls	-	-	-	-	Covered	T2,T3,T27
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T23,T20,T53

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T4,T17,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[0].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244327482	131722	0	0
FpvSecCmErrorStEscalate_A	244327482	132572	0	0
u_state_regs_A	244282957	244130360	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	131722	0	0
T4	2921	1060	0	0
T5	882	384	0	0
T6	0	350	0	0
T9	3859	0	0	0
T15	0	1072	0	0
T16	0	1158	0	0
T17	1861	0	0	0
T20	0	13872	0	0
T23	2175	1076	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1141	0	0
T53	0	1068	0	0
T54	0	385	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	132572	0	0
T4	2921	1061	0	0
T5	882	385	0	0
T6	0	351	0	0
T9	3859	0	0	0
T15	0	1073	0	0
T16	0	1159	0	0
T17	1861	0	0	0
T20	0	14052	0	0
T23	2175	1077	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1142	0	0
T53	0	1069	0	0
T54	0	386	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244282957	244130360	0	0
T1	1086	1022	0	0
T2	10270	9787	0	0
T3	2351	2267	0	0
T4	1739	1547	0	0
T5	740	637	0	0
T9	3859	3783	0	0
T17	1861	1804	0	0
T23	2013	1844	0	0
T27	4793	4733	0	0
T28	4014	3961	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T9,T29
DataWait	75	Covered	T28,T9,T29
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T2,T3,T4
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T28,T9,T29
DataWait->AckPls	80	Covered	T28,T9,T29
DataWait->Disabled	107	Covered	T37,T58,T82
DataWait->Error	99	Covered	T155,T86,T57
Disabled->EndPointClear	63	Covered	T2,T3,T4
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T36,T109,T110
EndPointClear->Error	99	Covered	T20,T97,T151
EndPointClear->Idle	68	Covered	T2,T3,T4
Idle->DataWait	75	Covered	T28,T9,T29
Idle->Disabled	107	Covered	T2,T4,T17
Idle->Error	99	Covered	T4,T5,T23

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T4
Idle	-	1	1	-	Covered	T28,T9,T29
Idle	-	1	0	-	Covered	T28,T9,T29
Idle	-	0	-	-	Covered	T2,T3,T4
DataWait	-	-	-	1	Covered	T28,T9,T29
DataWait	-	-	-	0	Covered	T28,T9,T29
AckPls	-	-	-	-	Covered	T28,T9,T29
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T4,T17,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[4].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244327482	134072	0	0
FpvSecCmErrorStEscalate_A	244327482	134922	0	0
u_state_regs_A	244327482	244174885	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134072	0	0
T4	2921	1060	0	0
T5	882	384	0	0
T6	0	350	0	0
T9	3859	0	0	0
T15	0	1072	0	0
T16	0	1158	0	0
T17	1861	0	0	0
T20	0	13872	0	0
T23	2175	1126	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1141	0	0
T53	0	1118	0	0
T54	0	385	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134922	0	0
T4	2921	1061	0	0
T5	882	385	0	0
T6	0	351	0	0
T9	3859	0	0	0
T15	0	1073	0	0
T16	0	1159	0	0
T17	1861	0	0	0
T20	0	14052	0	0
T23	2175	1127	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1142	0	0
T53	0	1119	0	0
T54	0	386	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	244174885	0	0
T1	1086	1022	0	0
T2	10270	9787	0	0
T3	2351	2267	0	0
T4	2921	2729	0	0
T5	882	779	0	0
T9	3859	3783	0	0
T17	1861	1804	0	0
T23	2175	2006	0	0
T27	4793	4733	0	0
T28	4014	3961	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	12	85.71
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T14,T29,T30
DataWait	75	Covered	T14,T29,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T2,T3,T4
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Not Covered
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T14,T29,T30
DataWait->AckPls	80	Covered	T14,T29,T30
DataWait->Disabled	107	Covered	T105,T156,T157
DataWait->Error	99	Covered	T158,T159
Disabled->EndPointClear	63	Covered	T2,T3,T4
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T36,T109,T110
EndPointClear->Error	99	Covered	T20,T97,T151
EndPointClear->Idle	68	Covered	T2,T3,T4
Idle->DataWait	75	Covered	T14,T29,T30
Idle->Disabled	107	Covered	T2,T4,T17
Idle->Error	99	Covered	T4,T5,T23

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T4
Idle	-	1	1	-	Covered	T14,T29,T30
Idle	-	1	0	-	Covered	T14,T29,T30
Idle	-	0	-	-	Covered	T2,T3,T4
DataWait	-	-	-	1	Covered	T14,T29,T30
DataWait	-	-	-	0	Covered	T14,T29,T30
AckPls	-	-	-	-	Covered	T14,T29,T30
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T4,T17,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[5].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244327482	134072	0	0
FpvSecCmErrorStEscalate_A	244327482	134922	0	0
u_state_regs_A	244327482	244174885	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134072	0	0
T4	2921	1060	0	0
T5	882	384	0	0
T6	0	350	0	0
T9	3859	0	0	0
T15	0	1072	0	0
T16	0	1158	0	0
T17	1861	0	0	0
T20	0	13872	0	0
T23	2175	1126	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1141	0	0
T53	0	1118	0	0
T54	0	385	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134922	0	0
T4	2921	1061	0	0
T5	882	385	0	0
T6	0	351	0	0
T9	3859	0	0	0
T15	0	1073	0	0
T16	0	1159	0	0
T17	1861	0	0	0
T20	0	14052	0	0
T23	2175	1127	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1142	0	0
T53	0	1119	0	0
T54	0	386	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	244174885	0	0
T1	1086	1022	0	0
T2	10270	9787	0	0
T3	2351	2267	0	0
T4	2921	2729	0	0
T5	882	779	0	0
T9	3859	3783	0	0
T17	1861	1804	0	0
T23	2175	2006	0	0
T27	4793	4733	0	0
T28	4014	3961	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T17,T14
DataWait	75	Covered	T28,T17,T14
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T2,T3,T4
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T149
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T28,T17,T14
DataWait->AckPls	80	Covered	T28,T17,T14
DataWait->Disabled	107	Covered	T160,T161,T162
DataWait->Error	99	Covered	T53,T41,T100
Disabled->EndPointClear	63	Covered	T2,T3,T4
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T36,T109,T110
EndPointClear->Error	99	Covered	T20,T97,T151
EndPointClear->Idle	68	Covered	T2,T3,T4
Idle->DataWait	75	Covered	T28,T17,T14
Idle->Disabled	107	Covered	T2,T4,T17
Idle->Error	99	Covered	T4,T5,T23

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T4
Idle	-	1	1	-	Covered	T28,T17,T14
Idle	-	1	0	-	Covered	T28,T17,T15
Idle	-	0	-	-	Covered	T2,T3,T4
DataWait	-	-	-	1	Covered	T28,T17,T14
DataWait	-	-	-	0	Covered	T28,T17,T14
AckPls	-	-	-	-	Covered	T28,T17,T14
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T4,T17,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[1].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244327482	134072	0	0
FpvSecCmErrorStEscalate_A	244327482	134922	0	0
u_state_regs_A	244327482	244174885	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134072	0	0
T4	2921	1060	0	0
T5	882	384	0	0
T6	0	350	0	0
T9	3859	0	0	0
T15	0	1072	0	0
T16	0	1158	0	0
T17	1861	0	0	0
T20	0	13872	0	0
T23	2175	1126	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1141	0	0
T53	0	1118	0	0
T54	0	385	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134922	0	0
T4	2921	1061	0	0
T5	882	385	0	0
T6	0	351	0	0
T9	3859	0	0	0
T15	0	1073	0	0
T16	0	1159	0	0
T17	1861	0	0	0
T20	0	14052	0	0
T23	2175	1127	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1142	0	0
T53	0	1119	0	0
T54	0	386	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	244174885	0	0
T1	1086	1022	0	0
T2	10270	9787	0	0
T3	2351	2267	0	0
T4	2921	2729	0	0
T5	882	779	0	0
T9	3859	3783	0	0
T17	1861	1804	0	0
T23	2175	2006	0	0
T27	4793	4733	0	0
T28	4014	3961	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T5,T10
DataWait	75	Covered	T28,T5,T10
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T2,T3,T4
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T163
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T28,T5,T10
DataWait->AckPls	80	Covered	T28,T5,T10
DataWait->Disabled	107	Covered	T164,T165,T166
DataWait->Error	99	Covered	T87,T167,T168
Disabled->EndPointClear	63	Covered	T2,T3,T4
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T36,T109,T110
EndPointClear->Error	99	Covered	T20,T97,T151
EndPointClear->Idle	68	Covered	T2,T3,T4
Idle->DataWait	75	Covered	T28,T5,T10
Idle->Disabled	107	Covered	T2,T4,T17
Idle->Error	99	Covered	T4,T5,T23

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T4
Idle	-	1	1	-	Covered	T28,T5,T10
Idle	-	1	0	-	Covered	T28,T5,T10
Idle	-	0	-	-	Covered	T2,T3,T4
DataWait	-	-	-	1	Covered	T28,T5,T10
DataWait	-	-	-	0	Covered	T28,T10,T14
AckPls	-	-	-	-	Covered	T28,T5,T10
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T4,T17,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[2].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244327482	134072	0	0
FpvSecCmErrorStEscalate_A	244327482	134922	0	0
u_state_regs_A	244327482	244174885	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134072	0	0
T4	2921	1060	0	0
T5	882	384	0	0
T6	0	350	0	0
T9	3859	0	0	0
T15	0	1072	0	0
T16	0	1158	0	0
T17	1861	0	0	0
T20	0	13872	0	0
T23	2175	1126	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1141	0	0
T53	0	1118	0	0
T54	0	385	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134922	0	0
T4	2921	1061	0	0
T5	882	385	0	0
T6	0	351	0	0
T9	3859	0	0	0
T15	0	1073	0	0
T16	0	1159	0	0
T17	1861	0	0	0
T20	0	14052	0	0
T23	2175	1127	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1142	0	0
T53	0	1119	0	0
T54	0	386	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	244174885	0	0
T1	1086	1022	0	0
T2	10270	9787	0	0
T3	2351	2267	0	0
T4	2921	2729	0	0
T5	882	779	0	0
T9	3859	3783	0	0
T17	1861	1804	0	0
T23	2175	2006	0	0
T27	4793	4733	0	0
T28	4014	3961	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T9,T23
DataWait	75	Covered	T28,T9,T23
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T2,T3,T4
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T115
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T28,T9,T23
DataWait->AckPls	80	Covered	T28,T9,T23
DataWait->Disabled	107	Covered	T81,T103,T65
DataWait->Error	99	Covered	T96,T169,T170
Disabled->EndPointClear	63	Covered	T2,T3,T4
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T36,T109,T110
EndPointClear->Error	99	Covered	T20,T97,T151
EndPointClear->Idle	68	Covered	T2,T3,T4
Idle->DataWait	75	Covered	T28,T9,T23
Idle->Disabled	107	Covered	T2,T4,T17
Idle->Error	99	Covered	T4,T5,T23

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T4
Idle	-	1	1	-	Covered	T28,T9,T23
Idle	-	1	0	-	Covered	T28,T9,T23
Idle	-	0	-	-	Covered	T2,T3,T4
DataWait	-	-	-	1	Covered	T28,T9,T23
DataWait	-	-	-	0	Covered	T28,T9,T14
AckPls	-	-	-	-	Covered	T28,T9,T23
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T4,T17,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[3].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244327482	134072	0	0
FpvSecCmErrorStEscalate_A	244327482	134922	0	0
u_state_regs_A	244327482	244174885	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134072	0	0
T4	2921	1060	0	0
T5	882	384	0	0
T6	0	350	0	0
T9	3859	0	0	0
T15	0	1072	0	0
T16	0	1158	0	0
T17	1861	0	0	0
T20	0	13872	0	0
T23	2175	1126	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1141	0	0
T53	0	1118	0	0
T54	0	385	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134922	0	0
T4	2921	1061	0	0
T5	882	385	0	0
T6	0	351	0	0
T9	3859	0	0	0
T15	0	1073	0	0
T16	0	1159	0	0
T17	1861	0	0	0
T20	0	14052	0	0
T23	2175	1127	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1142	0	0
T53	0	1119	0	0
T54	0	386	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	244174885	0	0
T1	1086	1022	0	0
T2	10270	9787	0	0
T3	2351	2267	0	0
T4	2921	2729	0	0
T5	882	779	0	0
T9	3859	3783	0	0
T17	1861	1804	0	0
T23	2175	2006	0	0
T27	4793	4733	0	0
T28	4014	3961	0	0

Line Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
TOTAL		32	32	100.00
ALWAYS	52	3	3	100.00
ALWAYS	55	29	29	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
52	3	3
55	1	1
56	1	1
57	1	1
58	1	1
59	1	1
60	1	1
62	1	1
63	1	1
64	1	1
			MISSING_ELSE
68	1	1
71	1	1
72	1	1
73	1	1
			MISSING_ELSE
75	1	1
			MISSING_ELSE
79	1	1
80	1	1
			MISSING_ELSE
84	1	1
85	1	1
88	1	1
98	1	1
99	1	1
101	1	1
102	1	1
103	1	1
104	1	1
107	1	1
109	1	1
110	1	1
111	1	1
			MISSING_ELSE

---

Cond Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Covered	Percent
Conditions	3	3	100.00
Logical	3	3	100.00
Non-Logical	0	0
Event	0	0

 LINE       104
 EXPRESSION (((!enable_i)) && (state_q inside {EndPointClear, Idle, DataWait, AckPls}))
             ------1------    ----------------------------2---------------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T3
1	1	Covered	T4,T17,T9

---

FSM Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

Summary for FSM :: state_q

	Total	Covered	Percent
States	6	6	100.00	(Not included in score)
Transitions	14	13	92.86
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
AckPls	80	Covered	T28,T14,T30
DataWait	75	Covered	T28,T14,T30
Disabled	107	Covered	T1,T2,T3
EndPointClear	63	Covered	T2,T3,T4
Error	99	Covered	T4,T5,T23
Idle	68	Covered	T2,T3,T4

transitions	Line No.	Covered	Tests
AckPls->Disabled	107	Covered	T150
AckPls->Error	99	Not Covered
AckPls->Idle	85	Covered	T28,T14,T30
DataWait->AckPls	80	Covered	T28,T14,T30
DataWait->Disabled	107	Covered	T64,T171,T172
DataWait->Error	99	Covered	T173
Disabled->EndPointClear	63	Covered	T2,T3,T4
Disabled->Error	99	Covered	T20,T21,T22
EndPointClear->Disabled	107	Covered	T36,T109,T110
EndPointClear->Error	99	Covered	T20,T97,T151
EndPointClear->Idle	68	Covered	T2,T3,T4
Idle->DataWait	75	Covered	T28,T14,T30
Idle->Disabled	107	Covered	T2,T4,T17
Idle->Error	99	Covered	T4,T5,T23

---

Branch Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Line No.	Total	Covered	Percent
Branches		16	16	100.00
IF	52	2	2	100.00
CASE	60	11	11	100.00
IF	98	3	3	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_ack_sm.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	52	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	60	case (state_q)
-2-:	62	if (enable_i)
-3-:	71	if (req_i)
-4-:	72	if (fifo_not_empty_i)
-5-:	79	if (fifo_not_empty_i)

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
Disabled	1	-	-	-	Covered	T2,T3,T4
Disabled	0	-	-	-	Covered	T1,T2,T3
EndPointClear	-	-	-	-	Covered	T2,T3,T4
Idle	-	1	1	-	Covered	T28,T14,T30
Idle	-	1	0	-	Covered	T28,T14,T30
Idle	-	0	-	-	Covered	T2,T3,T4
DataWait	-	-	-	1	Covered	T28,T14,T30
DataWait	-	-	-	0	Covered	T28,T14,T30
AckPls	-	-	-	-	Covered	T28,T14,T30
Error	-	-	-	-	Covered	T4,T5,T23
default	-	-	-	-	Covered	T20,T21,T22

	LineNo.	Expression
-1-:	98	if (local_escalate_i)
-2-:	104	if (((!enable_i) && (state_q inside {EndPointClear, Idle, DataWait, AckPls})))

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T4,T5,T23
0	1	Covered	T4,T17,T9
0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.gen_ep_blk[6].u_edn_ack_sm_ep

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AckSmErrorStStable_A	244327482	134072	0	0
FpvSecCmErrorStEscalate_A	244327482	134922	0	0
u_state_regs_A	244327482	244174885	0	0

AckSmErrorStStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134072	0	0
T4	2921	1060	0	0
T5	882	384	0	0
T6	0	350	0	0
T9	3859	0	0	0
T15	0	1072	0	0
T16	0	1158	0	0
T17	1861	0	0	0
T20	0	13872	0	0
T23	2175	1126	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1141	0	0
T53	0	1118	0	0
T54	0	385	0	0

FpvSecCmErrorStEscalate_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	134922	0	0
T4	2921	1061	0	0
T5	882	385	0	0
T6	0	351	0	0
T9	3859	0	0	0
T15	0	1073	0	0
T16	0	1159	0	0
T17	1861	0	0	0
T20	0	14052	0	0
T23	2175	1127	0	0
T24	905036	0	0	0
T27	4793	0	0	0
T28	4014	0	0	0
T31	23441	0	0	0
T44	1957	0	0	0
T52	0	1142	0	0
T53	0	1119	0	0
T54	0	386	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	244327482	244174885	0	0
T1	1086	1022	0	0
T2	10270	9787	0	0
T3	2351	2267	0	0
T4	2921	2729	0	0
T5	882	779	0	0
T9	3859	3783	0	0
T17	1861	1804	0	0
T23	2175	2006	0	0
T27	4793	4733	0	0
T28	4014	3961	0	0