Module Definition
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Module : edn_core
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.49 100.00 89.95 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.u_edn_core 97.49 100.00 89.95 100.00 100.00



Module Instance : tb.dut.u_edn_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.49 100.00 89.95 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
90.84 99.92 92.15 71.29 83.24 99.55 98.88


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
83.59 83.33 100.00 67.44 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_ep_blk[0].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[0].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[1].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[1].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[2].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[2].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[3].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[3].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[4].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[4].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[5].u_edn_ack_sm_ep 97.14 100.00 100.00 85.71 100.00 100.00
gen_ep_blk[5].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
gen_ep_blk[6].u_edn_ack_sm_ep 98.57 100.00 100.00 92.86 100.00 100.00
gen_ep_blk[6].u_prim_packer_fifo_ep 98.81 100.00 95.24 100.00 100.00
u_edn_main_sm 94.93 100.00 100.00 74.67 100.00 100.00
u_intr_hw_edn_cmd_req_done 100.00 100.00 100.00 100.00 100.00
u_intr_hw_edn_fatal_err 100.00 100.00 100.00 100.00 100.00
u_prim_arbiter_ppc_packer_arb 95.16 95.00 92.31 100.00 93.33
u_prim_count_max_reqs_cntr 71.29 71.29
u_prim_edge_detector_recov_alert 100.00 100.00 100.00 100.00
u_prim_fifo_sync_gencmd 97.12 100.00 88.46 100.00 100.00
u_prim_fifo_sync_rescmd 97.12 100.00 88.46 100.00 100.00
u_prim_mubi4_sync_auto_req_mode 100.00 100.00 100.00
u_prim_mubi4_sync_boot_req_mode 100.00 100.00 100.00
u_prim_mubi4_sync_cmd_fifo_rst 100.00 100.00 100.00
u_prim_mubi4_sync_edn_enable 100.00 100.00 100.00
u_prim_packer_fifo_cs 95.24 100.00 95.24 85.71 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : edn_core
Line No.TotalCoveredPercent
TOTAL253253100.00
ALWAYS2153636100.00
CONT_ASSIGN29011100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN30011100.00
CONT_ASSIGN30611100.00
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CONT_ASSIGN32111100.00
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CONT_ASSIGN36411100.00
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CONT_ASSIGN36811100.00
CONT_ASSIGN37011100.00
CONT_ASSIGN37111100.00
CONT_ASSIGN37411100.00
CONT_ASSIGN39311100.00
CONT_ASSIGN39611100.00
CONT_ASSIGN40011100.00
CONT_ASSIGN40911100.00
CONT_ASSIGN41011100.00
CONT_ASSIGN41111100.00
CONT_ASSIGN41211100.00
CONT_ASSIGN41511100.00
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CONT_ASSIGN41511100.00
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CONT_ASSIGN41511100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN41511100.00
CONT_ASSIGN43011100.00
CONT_ASSIGN43111100.00
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CONT_ASSIGN43311100.00
CONT_ASSIGN43611100.00
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CONT_ASSIGN43611100.00
CONT_ASSIGN45011100.00
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CONT_ASSIGN49011100.00
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CONT_ASSIGN54811100.00
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CONT_ASSIGN56911100.00
CONT_ASSIGN57011100.00
CONT_ASSIGN57711100.00
CONT_ASSIGN57811100.00
CONT_ASSIGN58911100.00
CONT_ASSIGN59011100.00
CONT_ASSIGN59511100.00
CONT_ASSIGN59611100.00
CONT_ASSIGN60211100.00
CONT_ASSIGN60311100.00
CONT_ASSIGN61211100.00
CONT_ASSIGN61311100.00
CONT_ASSIGN62211100.00
CONT_ASSIGN62311100.00
CONT_ASSIGN64711100.00
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CONT_ASSIGN65311100.00
CONT_ASSIGN65711100.00
CONT_ASSIGN65911100.00
CONT_ASSIGN66111100.00
CONT_ASSIGN68711100.00
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CONT_ASSIGN69711100.00
CONT_ASSIGN69911100.00
CONT_ASSIGN70111100.00
CONT_ASSIGN76011100.00
CONT_ASSIGN76411100.00
CONT_ASSIGN76711100.00
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CONT_ASSIGN78211100.00
CONT_ASSIGN78311100.00
CONT_ASSIGN78411100.00
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CONT_ASSIGN87511100.00
CONT_ASSIGN88111100.00
CONT_ASSIGN88411100.00
CONT_ASSIGN88511100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN91011100.00
CONT_ASSIGN91011100.00
CONT_ASSIGN91011100.00
CONT_ASSIGN91011100.00
CONT_ASSIGN91011100.00
CONT_ASSIGN91011100.00
CONT_ASSIGN91011100.00
CONT_ASSIGN91311100.00
CONT_ASSIGN91311100.00
CONT_ASSIGN91311100.00
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CONT_ASSIGN91911100.00
CONT_ASSIGN91911100.00
CONT_ASSIGN91911100.00
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CONT_ASSIGN92011100.00
CONT_ASSIGN92011100.00
CONT_ASSIGN92011100.00
CONT_ASSIGN92011100.00
CONT_ASSIGN92011100.00
CONT_ASSIGN92011100.00
CONT_ASSIGN92011100.00
CONT_ASSIGN94011100.00
CONT_ASSIGN95611100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
215 1 1
216 1 1
217 1 1
218 1 1
219 1 1
220 1 1
221 1 1
222 1 1
223 1 1
224 1 1
225 1 1
226 1 1
227 1 1
228 1 1
229 1 1
230 1 1
231 1 1
232 1 1
234 1 1
235 1 1
236 1 1
237 1 1
238 1 1
239 1 1
240 1 1
241 1 1
242 1 1
243 1 1
244 1 1
245 1 1
246 1 1
247 1 1
248 1 1
249 1 1
250 1 1
251 1 1
290 1 1
295 1 1
300 1 1
306 1 1
308 1 1
310 1 1
312 1 1
314 1 1
317 1 1
321 1 1
325 1 1
333 1 1
336 1 1
339 1 1
342 1 1
345 1 1
347 1 1
348 1 1
353 1 1
356 1 1
359 1 1
364 31 31
368 1 1
370 1 1
371 1 1
374 1 1
393 1 1
396 1 1
400 1 1
409 1 1
410 1 1
411 1 1
412 1 1
415 19 19
430 1 1
431 1 1
432 1 1
433 1 1
436 3 3
450 1 1
457 1 1
458 1 1
459 1 1
460 1 1
461 1 1
476 1 1
477 1 1
479 1 1
480 1 1
482 1 1
483 1 1
485 1 1
486 1 1
488 1 1
489 1 1
490 1 1
493 1 1
502 1 1
509 1 1
513 1 1
529 1 1
537 1 1
538 1 1
543 1 1
544 1 1
548 1 1
558 1 1
559 1 1
569 1 1
570 1 1
577 1 1
578 1 1
589 1 1
590 1 1
595 1 1
596 1 1
602 1 1
603 1 1
612 1 1
613 1 1
622 1 1
623 1 1
647 1 1
649 1 1
653 1 1
657 1 1
659 1 1
661 1 1
687 1 1
689 1 1
693 1 1
697 1 1
699 1 1
701 1 1
760 1 1
764 1 1
767 1 1
777 1 1
782 1 1
783 1 1
784 1 1
785 1 1
788 1 1
824 7 7
848 1 1
849 1 1
851 1 1
852 1 1
853 1 1
854 1 1
856 1 1
871 1 1
873 1 1
875 1 1
881 1 1
884 1 1
885 1 1
909 7 7
910 7 7
913 7 7
916 7 7
919 7 7
920 7 7
940 1 1
956 1 1


Cond Coverage for Module : edn_core
TotalCoveredPercent
Conditions61755589.95
Logical61755589.95
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
290-76091.61
760-95685.37

Branch Coverage for Module : edn_core
Line No.TotalCoveredPercent
Branches 104 104 100.00
TERNARY 493 6 6 100.00
TERNARY 502 4 4 100.00
TERNARY 513 7 7 100.00
TERNARY 529 5 5 100.00
TERNARY 548 6 6 100.00
TERNARY 559 6 6 100.00
TERNARY 570 3 3 100.00
TERNARY 578 4 4 100.00
TERNARY 590 3 3 100.00
TERNARY 596 3 3 100.00
TERNARY 603 5 5 100.00
TERNARY 613 5 5 100.00
TERNARY 623 2 2 100.00
TERNARY 649 2 2 100.00
TERNARY 653 2 2 100.00
TERNARY 689 2 2 100.00
TERNARY 693 2 2 100.00
TERNARY 767 6 6 100.00
TERNARY 856 3 3 100.00
TERNARY 873 2 2 100.00
TERNARY 875 3 3 100.00
TERNARY 913 3 3 100.00
TERNARY 913 3 3 100.00
TERNARY 913 3 3 100.00
TERNARY 913 3 3 100.00
TERNARY 913 3 3 100.00
TERNARY 913 3 3 100.00
TERNARY 913 3 3 100.00
IF 215 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 493 ((!edn_enable_fo[CsrngCmdReq])) ? -2-: 493 (boot_wr_ins_cmd) ? -3-: 493 (boot_wr_gen_cmd) ? -4-: 493 (boot_wr_uni_cmd) ? -5-: 493 (sw_cmd_req_load) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T3,T4,T28
0 0 1 - - Covered T3,T4,T28
0 0 0 1 - Covered T3,T28,T55
0 0 0 0 1 Covered T2,T3,T27
0 0 0 0 0 Covered T2,T3,T4


LineNo. Expression -1-: 502 ((!edn_enable_fo[CsrngCmdReqValid])) ? -2-: 502 (cs_cmd_handshake) ? -3-: 502 ((((sw_cmd_req_load || boot_wr_ins_cmd) || boot_wr_gen_cmd) || boot_wr_uni_cmd)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T4
0 0 1 Covered T2,T3,T4
0 0 0 Covered T2,T3,T4


LineNo. Expression -1-: 513 ((!edn_enable_fo[CsrngCmdReqOut])) ? -2-: 513 ((send_rescmd || capt_rescmd_fifo_cnt)) ? -3-: 513 (sfifo_rescmd_pop) ? -4-: 513 ((send_gencmd || capt_gencmd_fifo_cnt)) ? -5-: 513 (sfifo_gencmd_pop) ? -6-: 513 ((cs_cmd_req_vld_q && (!cs_cmd_handshake))) ?

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 1 - - - Covered T9,T10,T14
0 1 0 - - - Covered T9,T10,T14
0 0 - 1 1 - Covered T9,T10,T6
0 0 - 1 0 - Covered T9,T10,T14
0 0 - 0 - 1 Covered T2,T3,T4
0 0 - 0 - 0 Covered T2,T3,T4


LineNo. Expression -1-: 529 ((!edn_enable_fo[CsrngCmdReqValidOut])) ? -2-: 529 (cmd_sent) ? -3-: 529 ((send_rescmd || capt_rescmd_fifo_cnt)) ? -4-: 529 ((send_gencmd || capt_gencmd_fifo_cnt)) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T9,T10,T14
0 0 1 - Covered T9,T10,T14
0 0 0 1 Covered T9,T10,T6
0 0 0 0 Covered T2,T3,T4


LineNo. Expression -1-: 548 ((!edn_enable_fo[SwCmdSts])) ? -2-: 548 ((!sw_cmd_valid)) ? -3-: 548 (sw_cmd_req_load) ? -4-: 548 (accept_sw_cmds_pulse) ? -5-: 548 (csrng_cmd_i.csrng_rsp_ack) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T3,T4,T28
0 0 1 - - Covered T2,T3,T27
0 0 0 1 - Covered T2,T3,T27
0 0 0 0 1 Covered T2,T3,T27
0 0 0 0 0 Covered T2,T3,T27


LineNo. Expression -1-: 559 ((!edn_enable_fo[SwCmdSts])) ? -2-: 559 ((!sw_cmd_valid)) ? -3-: 559 (sw_cmd_req_load) ? -4-: 559 (accept_sw_cmds_pulse) ? -5-: 559 (cs_cmd_handshake) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T3,T4,T28
0 0 1 - - Covered T2,T3,T27
0 0 0 1 - Covered T2,T3,T27
0 0 0 0 1 Covered T2,T3,T27
0 0 0 0 0 Covered T2,T3,T27


LineNo. Expression -1-: 570 ((!edn_enable_fo[SwCmdSts])) ? -2-: 570 ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T27
0 0 Covered T2,T3,T4


LineNo. Expression -1-: 578 ((!edn_enable_fo[SwCmdSts])) ? -2-: 578 (sw_cmd_req_load) ? -3-: 578 ((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ?

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T2,T3,T27
0 0 1 Covered T2,T3,T27
0 0 0 Covered T2,T3,T4


LineNo. Expression -1-: 590 ((main_sm_done_pulse || (!edn_enable_fo[HwCmdSts]))) ? -2-: 590 (boot_wr_ins_cmd) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T3,T4,T28
0 0 Covered T2,T3,T4


LineNo. Expression -1-: 596 ((main_sm_done_pulse || (!edn_enable_fo[HwCmdSts]))) ? -2-: 596 (auto_req_mode_busy) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T9,T10,T6
0 0 Covered T2,T3,T4


LineNo. Expression -1-: 603 ((!edn_enable_fo[HwCmdSts])) ? -2-: 603 (sw_cmd_valid) ? -3-: 603 ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)) ? -4-: 603 ((csrng_cmd_i.csrng_rsp_ack && csrng_cmd_i.csrng_rsp_sts)) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T2,T3,T27
0 0 1 - Covered T3,T4,T28
0 0 0 1 Covered T17,T18,T19
0 0 0 0 Covered T3,T4,T28


LineNo. Expression -1-: 613 ((!edn_enable_fo[HwCmdSts])) ? -2-: 613 (sw_cmd_valid) ? -3-: 613 ((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)) ? -4-: 613 (csrng_cmd_i.csrng_rsp_ack) ?

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T2,T3,T27
0 0 1 - Covered T3,T4,T28
0 0 0 1 Covered T3,T4,T28
0 0 0 0 Covered T3,T4,T28


LineNo. Expression -1-: 623 ((((edn_enable_fo[HwCmdSts] && (!sw_cmd_valid)) && cs_cmd_req_vld_out_q) && csrng_cmd_i.csrng_req_ready)) ?

Branches:
-1-StatusTests
1 Covered T3,T4,T28
0 Covered T1,T2,T3


LineNo. Expression -1-: 649 (rescmd_handshake) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 653 (auto_req_mode_busy) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 689 (gencmd_handshake) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T14
0 Covered T1,T2,T3


LineNo. Expression -1-: 693 (auto_req_mode_busy) ?

Branches:
-1-StatusTests
1 Covered T9,T10,T6
0 Covered T1,T2,T3


LineNo. Expression -1-: 767 ((!edn_enable_fo[CmdFifoCnt])) ? -2-: 767 ((cmd_fifo_rst_fo[3] || main_sm_done_pulse)) ? -3-: 767 (capt_gencmd_fifo_cnt) ? -4-: 767 (capt_rescmd_fifo_cnt) ? -5-: 767 ((sfifo_gencmd_pop || sfifo_rescmd_pop)) ?

Branches:
-1--2--3--4--5-StatusTests
1 - - - - Covered T1,T2,T3
0 1 - - - Covered T2,T3,T27
0 0 1 - - Covered T9,T10,T6
0 0 0 1 - Covered T9,T10,T14
0 0 0 0 1 Covered T9,T10,T14
0 0 0 0 0 Covered T2,T3,T4


LineNo. Expression -1-: 856 ((!edn_enable_fo[CsrngFipsEn])) ? -2-: 856 ((packer_cs_push && packer_cs_wready)) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T27
0 0 Covered T2,T3,T4


LineNo. Expression -1-: 873 (cs_rdata_capt_vld) ?

Branches:
-1-StatusTests
1 Covered T2,T3,T27
0 Covered T1,T2,T3


LineNo. Expression -1-: 875 ((!edn_enable_fo[CsrngDataVld])) ? -2-: 875 (cs_rdata_capt_vld) ?

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T2,T3,T27
0 0 Covered T2,T3,T4


LineNo. Expression -1-: 913 (packer_ep_clr[0]) ? -2-: 913 ((packer_ep_push[0] && packer_ep_wready[0])) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T2,T3,T27
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 913 (packer_ep_clr[1]) ? -2-: 913 ((packer_ep_push[1] && packer_ep_wready[1])) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T28,T17,T14
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 913 (packer_ep_clr[2]) ? -2-: 913 ((packer_ep_push[2] && packer_ep_wready[2])) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T28,T5,T10
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 913 (packer_ep_clr[3]) ? -2-: 913 ((packer_ep_push[3] && packer_ep_wready[3])) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T28,T9,T23
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 913 (packer_ep_clr[4]) ? -2-: 913 ((packer_ep_push[4] && packer_ep_wready[4])) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T28,T9,T29
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 913 (packer_ep_clr[5]) ? -2-: 913 ((packer_ep_push[5] && packer_ep_wready[5])) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T14,T29,T30
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 913 (packer_ep_clr[6]) ? -2-: 913 ((packer_ep_push[6] && packer_ep_wready[6])) ?

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T4
0 1 Covered T28,T14,T30
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 215 if ((!rst_ni))

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : edn_core
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CsErrAcceptNoEntropy_A 244327482 6923 0 0
CsErrIssueNoCommands_A 244327482 6923 0 0


CsErrAcceptNoEntropy_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 244327482 6923 0 0
T5 882 0 0 0
T9 3859 0 0 0
T15 1793 0 0 0
T16 2346 0 0 0
T17 1861 117 0 0
T18 0 129 0 0
T19 0 160 0 0
T23 2175 0 0 0
T24 905036 0 0 0
T31 23441 0 0 0
T39 1298 0 0 0
T44 1957 0 0 0
T60 0 117 0 0
T61 0 159 0 0
T62 0 117 0 0
T98 0 130 0 0
T99 0 145 0 0
T116 0 162 0 0
T145 0 117 0 0

CsErrIssueNoCommands_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 244327482 6923 0 0
T5 882 0 0 0
T9 3859 0 0 0
T15 1793 0 0 0
T16 2346 0 0 0
T17 1861 117 0 0
T18 0 129 0 0
T19 0 160 0 0
T23 2175 0 0 0
T24 905036 0 0 0
T31 23441 0 0 0
T39 1298 0 0 0
T44 1957 0 0 0
T60 0 117 0 0
T61 0 159 0 0
T62 0 117 0 0
T98 0 130 0 0
T99 0 145 0 0
T116 0 162 0 0
T145 0 117 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%