Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.59		83.33	100.00			67.44

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	83.59		83.33	100.00			67.44

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.59		83.33	100.00			67.44

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.04	98.27	93.64	96.79	82.08	96.87	96.58

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	90.57	99.92	92.20	70.79	82.08	99.55	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T17,T18,T19

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T20,T21
1	0	Covered	T3,T4,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1168	1168	100.00
Total Bits 0->1	584	584	100.00
Total Bits 1->0	584	584	100.00

Ports	69	69	100.00
Port Bits	1168	1168	100.00
Port Bits 0->1	584	584	100.00
Port Bits 1->0	584	584	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T3,T22,T9	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T12	Yes	T1,T3,T12	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T12	Yes	T1,T2,T9	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T22,T12	Yes	T1,T22,T12	INPUT
edn_i[2].edn_req	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T2,T26	Yes	T1,T2,T26	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T22,T27	Yes	T2,T22,T27	INPUT
edn_i[5].edn_req	Yes	Yes	T1,T2,T26	Yes	T1,T2,T26	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T9	Yes	T1,T2,T9	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T1,T22,T26	Yes	T1,T22,T12	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T22,T26,T15	Yes	T22,T12,T26	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T22,T12	Yes	T1,T22,T12	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T1,T2,T26	Yes	T1,T2,T12	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T1,T26,T28	Yes	T1,T2,T26	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T1,T2,T12	Yes	T1,T2,T12	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T2,T26	Yes	T1,T2,T26	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T1,T2,T26	Yes	T1,T2,T26	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T2,T26	Yes	T1,T2,T26	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T2,T22,T27	Yes	T2,T22,T27	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T2,T29,T30	Yes	T2,T27,T31	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T2,T22,T27	Yes	T2,T22,T27	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T1,T2,T32	Yes	T1,T2,T11	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T1,T2,T32	Yes	T1,T2,T26	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T1,T2,T26	Yes	T1,T2,T26	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T1,T26,T33	Yes	T1,T2,T22	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
csrng_cmd_i.csrng_rsp_sts	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T17,T18,T19	Yes	T17,T18,T19	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T34,T23,T35	Yes	T34,T23,T35	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T5,T34	Yes	T4,T5,T34	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	29	67.44
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	29	67.44

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	222267032	222110796	0	0
CsrngAppIfOut_A	222267032	222110796	0	0
FpvSecCmCntAlertCheck_A	222267032	123	0	0
FpvSecCmMainFsmCheck_A	222267032	80	0	0
FpvSecCmRegWeOnehotCheck_A	222267032	80	0	0
IntrEdnCmdReqDoneKnownO_A	222267032	222110796	0	0
TlAReadyKnownO_A	222267032	222110796	0	0
TlDValidKnownO_A	222267032	222110796	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	222267032	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	222267032	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	222267032	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	222267032	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	222267032	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	222267032	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	222267032	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	222267032	0	0	0
gen_edn_if_asserts[0].EdnDataStable_A	222267032	0	0	0
gen_edn_if_asserts[0].EdnEndPointOut_A	222267032	222110796	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	222267032	126045	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	222267032	0	0	0
gen_edn_if_asserts[1].EdnDataStable_A	222267032	0	0	0
gen_edn_if_asserts[1].EdnEndPointOut_A	222267032	222110796	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	222267032	126045	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	222267032	0	0	0
gen_edn_if_asserts[2].EdnDataStable_A	222267032	0	0	0
gen_edn_if_asserts[2].EdnEndPointOut_A	222267032	222110796	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	222267032	126045	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	222267032	0	0	0
gen_edn_if_asserts[3].EdnDataStable_A	222267032	0	0	0
gen_edn_if_asserts[3].EdnEndPointOut_A	222267032	222110796	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	222267032	126045	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	222267032	0	0	0
gen_edn_if_asserts[4].EdnDataStable_A	222267032	0	0	0
gen_edn_if_asserts[4].EdnEndPointOut_A	222267032	222110796	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	222267032	126045	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	222267032	0	0	0
gen_edn_if_asserts[5].EdnDataStable_A	222267032	0	0	0
gen_edn_if_asserts[5].EdnEndPointOut_A	222267032	222110796	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	222267032	126045	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	222267032	0	0	0
gen_edn_if_asserts[6].EdnDataStable_A	222267032	0	0	0
gen_edn_if_asserts[6].EdnEndPointOut_A	222267032	222110796	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	222267032	126045	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	123	0	0
T3	16750	10	0	0
T4	364	0	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	1	0	0
T16	0	1	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T36	0	1	0	0
T37	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	1192	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	80	0	0
T3	16750	10	0	0
T4	364	0	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T43	1192	0	0	0
T44	0	20	0	0
T45	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	80	0	0
T3	16750	10	0	0
T4	364	0	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T43	1192	0	0	0
T44	0	20	0	0
T45	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	80	0	0
T3	16750	10	0	0
T4	364	0	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T43	1192	0	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	80	0	0
T3	16750	10	0	0
T4	364	0	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T43	1192	0	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	80	0	0
T3	16750	10	0	0
T4	364	0	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T43	1192	0	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	80	0	0
T3	16750	10	0	0
T4	364	0	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T43	1192	0	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	80	0	0
T3	16750	10	0	0
T4	364	0	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T43	1192	0	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	80	0	0
T3	16750	10	0	0
T4	364	0	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T43	1192	0	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	80	0	0
T3	16750	10	0	0
T4	364	0	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T20	0	20	0	0
T21	0	10	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T43	1192	0	0	0
T44	0	20	0	0
T45	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	126045	0	0
T3	16750	5018	0	0
T4	364	7	0	0
T5	0	7	0	0
T6	0	470	0	0
T7	0	381	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	360	0	0
T16	0	524	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T29	0	17	0	0
T36	0	417	0	0
T43	1192	0	0	0
T46	0	310	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	126045	0	0
T3	16750	5018	0	0
T4	364	7	0	0
T5	0	7	0	0
T6	0	470	0	0
T7	0	381	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	360	0	0
T16	0	524	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T29	0	17	0	0
T36	0	417	0	0
T43	1192	0	0	0
T46	0	310	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	126045	0	0
T3	16750	5018	0	0
T4	364	7	0	0
T5	0	7	0	0
T6	0	470	0	0
T7	0	381	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	360	0	0
T16	0	524	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T29	0	17	0	0
T36	0	417	0	0
T43	1192	0	0	0
T46	0	310	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	126045	0	0
T3	16750	5018	0	0
T4	364	7	0	0
T5	0	7	0	0
T6	0	470	0	0
T7	0	381	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	360	0	0
T16	0	524	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T29	0	17	0	0
T36	0	417	0	0
T43	1192	0	0	0
T46	0	310	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	126045	0	0
T3	16750	5018	0	0
T4	364	7	0	0
T5	0	7	0	0
T6	0	470	0	0
T7	0	381	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	360	0	0
T16	0	524	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T29	0	17	0	0
T36	0	417	0	0
T43	1192	0	0	0
T46	0	310	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	126045	0	0
T3	16750	5018	0	0
T4	364	7	0	0
T5	0	7	0	0
T6	0	470	0	0
T7	0	381	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	360	0	0
T16	0	524	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T29	0	17	0	0
T36	0	417	0	0
T43	1192	0	0	0
T46	0	310	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	0	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	222110796	0	0
T1	2095	2043	0	0
T2	5363	5279	0	0
T3	16750	9280	0	0
T4	364	239	0	0
T9	4310	4217	0	0
T12	3004	2940	0	0
T17	2002	1928	0	0
T22	1815	1738	0	0
T26	2553	2492	0	0
T27	1457	1390	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222267032	126045	0	0
T3	16750	5018	0	0
T4	364	7	0	0
T5	0	7	0	0
T6	0	470	0	0
T7	0	381	0	0
T9	4310	0	0	0
T12	3004	0	0	0
T15	0	360	0	0
T16	0	524	0	0
T17	2002	0	0	0
T18	1913	0	0	0
T22	1815	0	0	0
T26	2553	0	0	0
T27	1457	0	0	0
T29	0	17	0	0
T36	0	417	0	0
T43	1192	0	0	0
T46	0	310	0	0