Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	222757451	10080453	0	0
boot_gen_cmd_rd_A	222757451	46036	0	0
boot_ins_cmd_rd_A	222757451	52449	0	0
ctrl_rd_A	222757451	46411	0	0
err_code_test_rd_A	222757451	52804	0	0
intr_enable_rd_A	222757451	53477	0	0
max_num_reqs_between_reseeds_rd_A	222757451	47261	0	0
regwen_rd_A	222757451	53434	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222757451	10080453	0	0
T23	501621	185411	0	0
T24	0	246328	0	0
T25	0	254950	0	0
T28	3295	0	0	0
T29	1291	0	0	0
T35	12620	0	0	0
T48	2454	0	0	0
T89	1933	0	0	0
T114	2280	0	0	0
T115	2688	0	0	0
T130	0	100201	0	0
T131	0	108201	0	0
T135	0	341109	0	0
T136	0	246235	0	0
T137	4222	0	0	0
T179	2158	0	0	0
T181	0	191689	0	0
T182	0	136418	0	0
T183	0	252365	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222757451	46036	0	0
T23	501621	2574	0	0
T28	3295	0	0	0
T29	1291	0	0	0
T35	12620	0	0	0
T48	2454	0	0	0
T89	1933	0	0	0
T114	2280	0	0	0
T115	2688	0	0	0
T137	4222	0	0	0
T179	2158	0	0	0
T184	0	3012	0	0
T185	0	96	0	0
T186	0	3793	0	0
T187	0	11896	0	0
T188	0	2870	0	0
T189	0	2083	0	0
T190	0	5679	0	0
T191	0	1891	0	0
T192	0	7068	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222757451	52449	0	0
T23	501621	3228	0	0
T28	3295	0	0	0
T29	1291	0	0	0
T35	12620	0	0	0
T48	2454	0	0	0
T89	1933	0	0	0
T114	2280	0	0	0
T115	2688	0	0	0
T137	4222	0	0	0
T179	2158	0	0	0
T184	0	3386	0	0
T185	0	92	0	0
T186	0	4506	0	0
T187	0	13397	0	0
T188	0	3102	0	0
T189	0	2286	0	0
T190	0	6539	0	0
T191	0	2016	0	0
T192	0	8108	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222757451	46411	0	0
T23	501621	2896	0	0
T28	3295	0	0	0
T29	1291	0	0	0
T35	12620	0	0	0
T48	2454	0	0	0
T89	1933	0	0	0
T102	0	9	0	0
T114	2280	0	0	0
T115	2688	0	0	0
T123	0	7	0	0
T137	4222	0	0	0
T179	2158	0	0	0
T184	0	2841	0	0
T185	0	93	0	0
T186	0	3687	0	0
T193	0	1	0	0
T194	0	3	0	0
T195	0	7	0	0
T196	0	2	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222757451	52804	0	0
T23	501621	3185	0	0
T28	3295	0	0	0
T29	1291	0	0	0
T35	12620	0	0	0
T48	2454	0	0	0
T89	1933	0	0	0
T114	2280	0	0	0
T115	2688	0	0	0
T137	4222	0	0	0
T179	2158	0	0	0
T184	0	3531	0	0
T185	0	133	0	0
T186	0	3973	0	0
T187	0	13512	0	0
T188	0	3346	0	0
T189	0	2521	0	0
T190	0	6872	0	0
T191	0	2013	0	0
T192	0	8008	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222757451	53477	0	0
T15	853	0	0	0
T16	1024	0	0	0
T23	501621	3289	0	0
T32	3734	0	0	0
T33	1328	0	0	0
T34	19836	138	0	0
T59	6563	0	0	0
T88	2436	0	0	0
T132	2080	0	0	0
T143	999	0	0	0
T184	0	3708	0	0
T185	0	271	0	0
T186	0	4461	0	0
T194	0	56	0	0
T197	0	36	0	0
T198	0	110	0	0
T199	0	43	0	0
T200	0	40	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222757451	47261	0	0
T23	501621	2617	0	0
T28	3295	0	0	0
T29	1291	0	0	0
T35	12620	0	0	0
T48	2454	0	0	0
T89	1933	0	0	0
T114	2280	0	0	0
T115	2688	0	0	0
T137	4222	0	0	0
T179	2158	0	0	0
T184	0	2839	0	0
T185	0	164	0	0
T186	0	3767	0	0
T187	0	12075	0	0
T188	0	3008	0	0
T189	0	2015	0	0
T190	0	5814	0	0
T191	0	1858	0	0
T192	0	7146	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222757451	53434	0	0
T23	501621	3372	0	0
T28	3295	0	0	0
T29	1291	0	0	0
T35	12620	0	0	0
T48	2454	0	0	0
T89	1933	0	0	0
T114	2280	0	0	0
T115	2688	0	0	0
T137	4222	0	0	0
T179	2158	0	0	0
T184	0	3302	0	0
T185	0	75	0	0
T186	0	4214	0	0
T187	0	13758	0	0
T188	0	3653	0	0
T189	0	2502	0	0
T190	0	5986	0	0
T191	0	2026	0	0
T192	0	7983	0	0