Module Definition
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Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.31 100.00 81.25 100.00 100.00 u_prim_fifo_sync_rescmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.31 100.00 81.25 100.00 100.00 u_prim_fifo_sync_gencmd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Module : prim_fifo_sync_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT19,T7,T14
11CoveredT7,T8,T9

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT57,T58,T35
10CoveredT7,T8,T13
11CoveredT57,T58,T60

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT57,T58,T35

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT57,T58,T35
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT57,T58,T35
1CoveredT1,T2,T3

Branch Coverage for Module : prim_fifo_sync_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T7,T8,T9
0 1 Covered T1,T2,T3
0 0 Covered T57,T58,T35


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T7,T8,T9
0 0 0 1 Covered T19,T7,T14
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T57,T58,T60
0 0 0 1 Covered T7,T8,T13
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT8,T9,T57
10CoveredT19,T7,T14
11CoveredT9,T56,T58

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT8,T9,T57

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT58,T60,T61
10CoveredT8,T57,T58
11CoveredT58,T60,T143

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT58,T60,T61

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T56,T61

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT9,T56,T61

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT58,T60,T61
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT58,T60,T61
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T9,T56,T61
0 1 Covered T1,T2,T3
0 0 Covered T58,T60,T61


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T9,T56,T58
0 0 0 1 Covered T19,T7,T14
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T58,T60,T143
0 0 0 1 Covered T57,T58,T35
0 0 0 0 Covered T1,T2,T3

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
TOTAL2727100.00
CONT_ASSIGN4111100.00
CONT_ASSIGN4211100.00
CONT_ASSIGN4611100.00
CONT_ASSIGN4711100.00
CONT_ASSIGN5111100.00
CONT_ASSIGN5211100.00
CONT_ASSIGN5511100.00
CONT_ASSIGN5611100.00
CONT_ASSIGN5911100.00
CONT_ASSIGN6111100.00
CONT_ASSIGN6811100.00
ALWAYS11388100.00
ALWAYS12588100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
41 1 1
42 1 1
46 1 1
47 1 1
51 1 1
52 1 1
55 1 1
56 1 1
59 1 1
61 1 1
68 1 1
113 1 1
114 1 1
115 1 1
116 1 1
117 1 1
118 1 1
119 1 1
120 1 1
MISSING_ELSE
125 1 1
126 1 1
127 1 1
128 1 1
129 1 1
130 1 1
131 1 1
132 1 1
MISSING_ELSE


Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt
TotalCoveredPercent
Conditions2020100.00
Logical2020100.00
Non-Logical00
Event00

 LINE       51
 EXPRESSION (incr_wptr_i & (wptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT7,T8,T9
10CoveredT19,T7,T14
11CoveredT7,T8,T9

 LINE       51
 SUB-EXPRESSION (wptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       52
 EXPRESSION (incr_rptr_i & (rptr_o == 4'((Depth - 1))))
             -----1-----   -------------2-------------
-1--2-StatusTests
01CoveredT57,T58,T35
10CoveredT7,T8,T13
11CoveredT57,T58,T60

 LINE       52
 SUB-EXPRESSION (rptr_o == 4'((Depth - 1)))
                -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT57,T58,T35

 LINE       59
 EXPRESSION (wptr_wrap_cnt_q == (rptr_wrap_cnt_q ^ {1'b1, {(WrapPtrW - 1) {1'b0}}}))
            ------------------------------------1-----------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       61
 EXPRESSION (wptr_wrap_cnt_q == rptr_wrap_cnt_q)
            ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       68
 EXPRESSION (full_o ? (4'(Depth)) : ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o)))))
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T8,T9

 LINE       68
 SUB-EXPRESSION ((wptr_wrap_msb == rptr_wrap_msb) ? ((4'(wptr_o) - 4'(rptr_o))) : (((4'(Depth) - 4'(rptr_o)) + 4'(wptr_o))))
                 ----------------1---------------
-1-StatusTests
0CoveredT57,T58,T35
1CoveredT1,T2,T3

 LINE       68
 SUB-EXPRESSION (wptr_wrap_msb == rptr_wrap_msb)
                ----------------1---------------
-1-StatusTests
0CoveredT57,T58,T35
1CoveredT1,T2,T3

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd.gen_normal_fifo.u_fifo_cnt
Line No.TotalCoveredPercent
Branches 13 13 100.00
TERNARY 68 3 3 100.00
IF 113 5 5 100.00
IF 125 5 5 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync_cnt.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 68 (full_o) ? -2-: 68 ((wptr_wrap_msb == rptr_wrap_msb)) ?

Branches:
-1--2-StatusTests
1 - Covered T7,T8,T9
0 1 Covered T1,T2,T3
0 0 Covered T57,T58,T35


LineNo. Expression -1-: 113 if ((!rst_ni)) -2-: 115 if (clr_i) -3-: 117 if (wptr_wrap_set) -4-: 119 if (incr_wptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T7,T8,T9
0 0 0 1 Covered T19,T7,T14
0 0 0 0 Covered T1,T2,T3


LineNo. Expression -1-: 125 if ((!rst_ni)) -2-: 127 if (clr_i) -3-: 129 if (rptr_wrap_set) -4-: 131 if (incr_rptr_i)

Branches:
-1--2--3--4-StatusTests
1 - - - Covered T1,T2,T3
0 1 - - Covered T1,T2,T3
0 0 1 - Covered T57,T58,T60
0 0 0 1 Covered T7,T8,T13
0 0 0 0 Covered T1,T2,T3

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%