Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	95.31	100.00	81.25			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	95.31	100.00	81.25			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T19,T7,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T113,T114,T115
1	1	0	Not Covered
1	1	1	Covered	T19,T7,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T55,T116,T117
1	0	1	Covered	T19,T7,T14
1	1	0	Not Covered
1	1	1	Covered	T7,T8,T13

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T19,T7,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T19,T7,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T19,T7,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	414997874	913174	0	0
DepthKnown_A	415366914	415075444	0	0
RvalidKnown_A	415366914	415075444	0	0
WreadyKnown_A	415366914	415075444	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	415366914	1001780	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	414997874	913174	0	0
T7	824	338	0	0
T8	0	296	0	0
T9	0	63	0	0
T13	0	881	0	0
T14	178	0	0	0
T22	1076964	0	0	0
T25	11838	0	0	0
T28	2800	0	0	0
T29	2250	0	0	0
T35	0	6171	0	0
T39	0	79	0	0
T56	0	39	0	0
T57	0	11389	0	0
T58	0	3254	0	0
T60	0	1774	0	0
T118	28738	0	0	0
T119	3614	0	0	0
T120	53288	0	0	0
T121	2546	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415366914	415075444	0	0
T1	4946	4836	0	0
T2	4320	4180	0	0
T3	2652	2528	0	0
T4	1780	1452	0	0
T5	7488	7258	0	0
T6	3346	3050	0	0
T19	2702	2374	0	0
T20	5484	5330	0	0
T21	22682	21408	0	0
T38	2282	2094	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415366914	415075444	0	0
T1	4946	4836	0	0
T2	4320	4180	0	0
T3	2652	2528	0	0
T4	1780	1452	0	0
T5	7488	7258	0	0
T6	3346	3050	0	0
T19	2702	2374	0	0
T20	5484	5330	0	0
T21	22682	21408	0	0
T38	2282	2094	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415366914	415075444	0	0
T1	4946	4836	0	0
T2	4320	4180	0	0
T3	2652	2528	0	0
T4	1780	1452	0	0
T5	7488	7258	0	0
T6	3346	3050	0	0
T19	2702	2374	0	0
T20	5484	5330	0	0
T21	22682	21408	0	0
T38	2282	2094	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	415366914	1001780	0	0
T7	5376	2295	0	0
T8	0	1306	0	0
T9	0	1354	0	0
T13	0	881	0	0
T14	1130	240	0	0
T15	0	269	0	0
T19	2702	260	0	0
T22	1076964	0	0	0
T25	11838	0	0	0
T28	2800	0	0	0
T37	5026	0	0	0
T44	2646	0	0	0
T56	0	1028	0	0
T57	0	11389	0	0
T58	0	3254	0	0
T118	28738	0	0	0
T119	3614	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T9,T56,T61
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T19,T7,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T113,T115
1	1	0	Not Covered
1	1	1	Covered	T19,T7,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T55,T116,T122
1	0	1	Covered	T19,T7,T14
1	1	0	Not Covered
1	1	1	Covered	T8,T57,T58

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T19,T7,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T19,T7,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T19,T7,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	207498937	452137	0	0
DepthKnown_A	207683457	207537722	0	0
RvalidKnown_A	207683457	207537722	0	0
WreadyKnown_A	207683457	207537722	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	207683457	496294	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207498937	452137	0	0
T7	412	126	0	0
T8	0	139	0	0
T9	0	31	0	0
T13	0	411	0	0
T14	89	0	0	0
T22	538482	0	0	0
T25	5919	0	0	0
T28	1400	0	0	0
T29	1125	0	0	0
T35	0	3076	0	0
T39	0	27	0	0
T56	0	9	0	0
T57	0	5685	0	0
T58	0	1581	0	0
T60	0	873	0	0
T118	14369	0	0	0
T119	1807	0	0	0
T120	26644	0	0	0
T121	1273	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	496294	0	0
T7	2688	1100	0	0
T8	0	621	0	0
T9	0	678	0	0
T13	0	411	0	0
T14	565	121	0	0
T15	0	137	0	0
T19	1351	136	0	0
T22	538482	0	0	0
T25	5919	0	0	0
T28	1400	0	0	0
T37	2513	0	0	0
T44	1323	0	0	0
T56	0	505	0	0
T57	0	5685	0	0
T58	0	1581	0	0
T118	14369	0	0	0
T119	1807	0	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T19,T7,T14

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T114,T123
1	1	0	Not Covered
1	1	1	Covered	T19,T7,T14

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T117,T124,T125
1	0	1	Covered	T19,T7,T14
1	1	0	Not Covered
1	1	1	Covered	T7,T8,T13

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T19,T7,T14
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T19,T7,T14

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T19,T7,T14
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	207498937	461037	0	0
DepthKnown_A	207683457	207537722	0	0
RvalidKnown_A	207683457	207537722	0	0
WreadyKnown_A	207683457	207537722	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	207683457	505486	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207498937	461037	0	0
T7	412	212	0	0
T8	0	157	0	0
T9	0	32	0	0
T13	0	470	0	0
T14	89	0	0	0
T22	538482	0	0	0
T25	5919	0	0	0
T28	1400	0	0	0
T29	1125	0	0	0
T35	0	3095	0	0
T39	0	52	0	0
T56	0	30	0	0
T57	0	5704	0	0
T58	0	1673	0	0
T60	0	901	0	0
T118	14369	0	0	0
T119	1807	0	0	0
T120	26644	0	0	0
T121	1273	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	207537722	0	0
T1	2473	2418	0	0
T2	2160	2090	0	0
T3	1326	1264	0	0
T4	890	726	0	0
T5	3744	3629	0	0
T6	1673	1525	0	0
T19	1351	1187	0	0
T20	2742	2665	0	0
T21	11341	10704	0	0
T38	1141	1047	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	207683457	505486	0	0
T7	2688	1195	0	0
T8	0	685	0	0
T9	0	676	0	0
T13	0	470	0	0
T14	565	119	0	0
T15	0	132	0	0
T19	1351	124	0	0
T22	538482	0	0	0
T25	5919	0	0	0
T28	1400	0	0	0
T37	2513	0	0	0
T44	1323	0	0	0
T56	0	523	0	0
T57	0	5704	0	0
T58	0	1673	0	0
T118	14369	0	0	0
T119	1807	0	0	0