Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	215396290	9462356	0	0
boot_gen_cmd_rd_A	215396290	56685	0	0
boot_ins_cmd_rd_A	215396290	65115	0	0
ctrl_rd_A	215396290	57277	0	0
err_code_test_rd_A	215396290	65700	0	0
intr_enable_rd_A	215396290	64481	0	0
max_num_reqs_between_reseeds_rd_A	215396290	57169	0	0
regwen_rd_A	215396290	65183	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215396290	9462356	0	0
T6	2632	0	0	0
T16	688001	290035	0	0
T17	489998	167554	0	0
T18	227561	128507	0	0
T20	2435	0	0	0
T22	1218	0	0	0
T26	736	0	0	0
T42	1267	0	0	0
T53	1003	0	0	0
T147	0	324731	0	0
T149	0	325703	0	0
T150	0	326168	0	0
T163	1562	0	0	0
T180	0	209151	0	0
T181	0	204118	0	0
T182	0	242068	0	0
T183	0	104321	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215396290	56685	0	0
T6	2632	0	0	0
T17	489998	4716	0	0
T18	227561	0	0	0
T20	2435	0	0	0
T22	1218	0	0	0
T26	736	0	0	0
T28	2624	0	0	0
T42	1267	0	0	0
T101	1962	0	0	0
T163	1562	0	0	0
T183	0	3012	0	0
T184	0	8808	0	0
T185	0	2029	0	0
T186	0	7694	0	0
T187	0	1306	0	0
T188	0	8188	0	0
T189	0	883	0	0
T190	0	423	0	0
T191	0	4355	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215396290	65115	0	0
T6	2632	0	0	0
T17	489998	5457	0	0
T18	227561	0	0	0
T20	2435	0	0	0
T22	1218	0	0	0
T26	736	0	0	0
T28	2624	0	0	0
T42	1267	0	0	0
T101	1962	0	0	0
T163	1562	0	0	0
T183	0	3727	0	0
T184	0	9575	0	0
T185	0	2130	0	0
T186	0	8962	0	0
T187	0	1479	0	0
T188	0	9078	0	0
T189	0	836	0	0
T190	0	629	0	0
T191	0	5249	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215396290	57277	0	0
T6	2632	0	0	0
T17	489998	4784	0	0
T18	227561	0	0	0
T20	2435	0	0	0
T22	1218	0	0	0
T26	736	0	0	0
T28	2624	0	0	0
T42	1267	0	0	0
T101	1962	0	0	0
T125	0	7	0	0
T145	0	3	0	0
T163	1562	0	0	0
T183	0	2950	0	0
T184	0	8934	0	0
T185	0	2264	0	0
T186	0	7525	0	0
T192	0	1	0	0
T193	0	7	0	0
T194	0	11	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215396290	65700	0	0
T6	2632	0	0	0
T17	489998	5267	0	0
T18	227561	0	0	0
T20	2435	0	0	0
T22	1218	0	0	0
T26	736	0	0	0
T28	2624	0	0	0
T42	1267	0	0	0
T101	1962	0	0	0
T163	1562	0	0	0
T183	0	3536	0	0
T184	0	9903	0	0
T185	0	2182	0	0
T186	0	8738	0	0
T187	0	1467	0	0
T188	0	9495	0	0
T189	0	949	0	0
T190	0	586	0	0
T191	0	5358	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215396290	64481	0	0
T6	2632	0	0	0
T17	489998	5125	0	0
T18	227561	0	0	0
T20	2435	0	0	0
T22	1218	0	0	0
T26	736	0	0	0
T28	2624	0	0	0
T42	1267	0	0	0
T101	1962	0	0	0
T145	0	30	0	0
T163	1562	0	0	0
T183	0	3665	0	0
T184	0	9384	0	0
T185	0	2376	0	0
T192	0	69	0	0
T193	0	120	0	0
T195	0	106	0	0
T196	0	61	0	0
T197	0	11	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215396290	57169	0	0
T6	2632	0	0	0
T17	489998	4784	0	0
T18	227561	0	0	0
T20	2435	0	0	0
T22	1218	0	0	0
T26	736	0	0	0
T28	2624	0	0	0
T42	1267	0	0	0
T101	1962	0	0	0
T163	1562	0	0	0
T183	0	3052	0	0
T184	0	9137	0	0
T185	0	1807	0	0
T186	0	7164	0	0
T187	0	1419	0	0
T188	0	7916	0	0
T189	0	772	0	0
T190	0	570	0	0
T191	0	4474	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	215396290	65183	0	0
T6	2632	0	0	0
T17	489998	5261	0	0
T18	227561	0	0	0
T20	2435	0	0	0
T22	1218	0	0	0
T26	736	0	0	0
T28	2624	0	0	0
T42	1267	0	0	0
T101	1962	0	0	0
T163	1562	0	0	0
T183	0	3592	0	0
T184	0	9706	0	0
T185	0	2188	0	0
T186	0	8645	0	0
T187	0	1253	0	0
T188	0	9400	0	0
T189	0	1051	0	0
T190	0	562	0	0
T191	0	5056	0	0