Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	95.31	100.00	81.25			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	95.31	100.00	81.25			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.31	100.00	81.25			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.92	100.00	91.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.49	100.00	89.95			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00			100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T25,T21,T53
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T60,T61
1	0	1	Covered	T3,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	429457880	1396464	0	0
DepthKnown_A	429810724	429490828	0	0
RvalidKnown_A	429810724	429490828	0	0
WreadyKnown_A	429810724	429490828	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	429810724	1483999	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429457880	1396464	0	0
T3	340	69	0	0
T4	66220	0	0	0
T5	0	47	0	0
T6	0	342	0	0
T7	3636	933	0	0
T8	4430	526	0	0
T9	4592	2024	0	0
T12	0	615	0	0
T19	15146	11567	0	0
T20	0	1636	0	0
T23	136	0	0	0
T25	976	0	0	0
T29	0	131	0	0
T44	3680	0	0	0
T45	240	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429810724	429490828	0	0
T1	1666	1280	0	0
T2	6688	6508	0	0
T3	1638	1306	0	0
T4	66220	36488	0	0
T7	3636	3500	0	0
T8	4430	4306	0	0
T9	4592	4400	0	0
T19	15146	14994	0	0
T23	738	512	0	0
T44	3680	3492	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429810724	429490828	0	0
T1	1666	1280	0	0
T2	6688	6508	0	0
T3	1638	1306	0	0
T4	66220	36488	0	0
T7	3636	3500	0	0
T8	4430	4306	0	0
T9	4592	4400	0	0
T19	15146	14994	0	0
T23	738	512	0	0
T44	3680	3492	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	429810724	429490828	0	0
T1	1666	1280	0	0
T2	6688	6508	0	0
T3	1638	1306	0	0
T4	66220	36488	0	0
T7	3636	3500	0	0
T8	4430	4306	0	0
T9	4592	4400	0	0
T19	15146	14994	0	0
T23	738	512	0	0
T44	3680	3492	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	429810724	1483999	0	0
T3	1638	669	0	0
T4	66220	0	0	0
T5	0	961	0	0
T7	3636	933	0	0
T8	4430	526	0	0
T9	4592	2024	0	0
T19	15146	11567	0	0
T21	0	35	0	0
T23	738	220	0	0
T25	4180	19	0	0
T43	0	7	0	0
T44	3680	0	0	0
T45	2400	366	0	0
T53	0	22	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T21,T53,T57
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T21,T53,T57
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T60
1	0	1	Covered	T3,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T7,T9,T19

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	214728940	693626	0	0
DepthKnown_A	214905362	214745414	0	0
RvalidKnown_A	214905362	214745414	0	0
WreadyKnown_A	214905362	214745414	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	214905362	736838	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214728940	693626	0	0
T3	170	29	0	0
T4	33110	0	0	0
T5	0	11	0	0
T6	0	136	0	0
T7	1818	469	0	0
T8	2215	269	0	0
T9	2296	1012	0	0
T12	0	308	0	0
T19	7573	5778	0	0
T20	0	801	0	0
T23	68	0	0	0
T25	488	0	0	0
T29	0	17	0	0
T44	1840	0	0	0
T45	120	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214905362	214745414	0	0
T1	833	640	0	0
T2	3344	3254	0	0
T3	819	653	0	0
T4	33110	18244	0	0
T7	1818	1750	0	0
T8	2215	2153	0	0
T9	2296	2200	0	0
T19	7573	7497	0	0
T23	369	256	0	0
T44	1840	1746	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214905362	214745414	0	0
T1	833	640	0	0
T2	3344	3254	0	0
T3	819	653	0	0
T4	33110	18244	0	0
T7	1818	1750	0	0
T8	2215	2153	0	0
T9	2296	2200	0	0
T19	7573	7497	0	0
T23	369	256	0	0
T44	1840	1746	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214905362	214745414	0	0
T1	833	640	0	0
T2	3344	3254	0	0
T3	819	653	0	0
T4	33110	18244	0	0
T7	1818	1750	0	0
T8	2215	2153	0	0
T9	2296	2200	0	0
T19	7573	7497	0	0
T23	369	256	0	0
T44	1840	1746	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	214905362	736838	0	0
T3	819	319	0	0
T4	33110	0	0	0
T5	0	458	0	0
T7	1818	469	0	0
T8	2215	269	0	0
T9	2296	1012	0	0
T19	7573	5778	0	0
T21	0	35	0	0
T23	369	111	0	0
T25	2090	0	0	0
T44	1840	0	0	0
T45	1200	184	0	0
T53	0	22	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	138	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
138	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	16	13	81.25
Logical	16	13	81.25
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T3,T7,T8

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T25
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T59,T61,T124
1	0	1	Covered	T3,T7,T8
1	1	0	Not Covered
1	1	1	Covered	T3,T7,T8

 LINE       138
 EXPRESSION (gen_normal_fifo.empty ? 'b0 : gen_normal_fifo.rdata_int)
             ----------1----------

-1-	Status	Tests
0	Covered	T3,T7,T8
1	Covered	T1,T2,T3

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		7	7	100.00
TERNARY	138	2	2	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	138	(gen_normal_fifo.empty) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T3,T7,T8

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	214728940	702838	0	0
DepthKnown_A	214905362	214745414	0	0
RvalidKnown_A	214905362	214745414	0	0
WreadyKnown_A	214905362	214745414	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	214905362	747161	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214728940	702838	0	0
T3	170	40	0	0
T4	33110	0	0	0
T5	0	36	0	0
T6	0	206	0	0
T7	1818	464	0	0
T8	2215	257	0	0
T9	2296	1012	0	0
T12	0	307	0	0
T19	7573	5789	0	0
T20	0	835	0	0
T23	68	0	0	0
T25	488	0	0	0
T29	0	114	0	0
T44	1840	0	0	0
T45	120	0	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214905362	214745414	0	0
T1	833	640	0	0
T2	3344	3254	0	0
T3	819	653	0	0
T4	33110	18244	0	0
T7	1818	1750	0	0
T8	2215	2153	0	0
T9	2296	2200	0	0
T19	7573	7497	0	0
T23	369	256	0	0
T44	1840	1746	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214905362	214745414	0	0
T1	833	640	0	0
T2	3344	3254	0	0
T3	819	653	0	0
T4	33110	18244	0	0
T7	1818	1750	0	0
T8	2215	2153	0	0
T9	2296	2200	0	0
T19	7573	7497	0	0
T23	369	256	0	0
T44	1840	1746	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214905362	214745414	0	0
T1	833	640	0	0
T2	3344	3254	0	0
T3	819	653	0	0
T4	33110	18244	0	0
T7	1818	1750	0	0
T8	2215	2153	0	0
T9	2296	2200	0	0
T19	7573	7497	0	0
T23	369	256	0	0
T44	1840	1746	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	214905362	747161	0	0
T3	819	350	0	0
T4	33110	0	0	0
T5	0	503	0	0
T7	1818	464	0	0
T8	2215	257	0	0
T9	2296	1012	0	0
T19	7573	5789	0	0
T23	369	109	0	0
T25	2090	19	0	0
T43	0	7	0	0
T44	1840	0	0	0
T45	1200	182	0	0