Unified Coverage Report :: Module :: edn_core

Module : edn_core

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.49	100.00	89.95			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core	97.49	100.00	89.95			100.00	100.00

---

Module Instance : tb.dut.u_edn_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.49	100.00	89.95			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.39	99.92	92.29	70.79	80.92	99.55	98.88

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.59		83.33	100.00			67.44	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_ep_blk[0].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[0].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[1].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[1].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[2].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[2].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[3].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[3].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[4].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[4].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[5].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[5].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
gen_ep_blk[6].u_edn_ack_sm_ep	97.14	100.00	100.00		85.71	100.00	100.00
gen_ep_blk[6].u_prim_packer_fifo_ep	98.81	100.00	95.24			100.00	100.00
u_edn_main_sm	94.93	100.00	100.00		74.67	100.00	100.00
u_intr_hw_edn_cmd_req_done	100.00	100.00	100.00			100.00	100.00
u_intr_hw_edn_fatal_err	100.00	100.00	100.00			100.00	100.00
u_prim_arbiter_ppc_packer_arb	95.16	95.00	92.31			100.00	93.33
u_prim_count_max_reqs_cntr	70.79			70.79
u_prim_edge_detector_recov_alert	100.00	100.00	100.00			100.00
u_prim_fifo_sync_gencmd	97.92	100.00	91.67			100.00	100.00
u_prim_fifo_sync_rescmd	97.92	100.00	91.67			100.00	100.00
u_prim_mubi4_sync_auto_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_boot_req_mode	100.00	100.00					100.00
u_prim_mubi4_sync_cmd_fifo_rst	100.00	100.00					100.00
u_prim_mubi4_sync_edn_enable	100.00	100.00					100.00
u_prim_packer_fifo_cs	95.24	100.00	95.24			85.71	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
TOTAL		253	253	100.00
ALWAYS	215	36	36	100.00
CONT_ASSIGN	290	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	300	1	1	100.00
CONT_ASSIGN	306	1	1	100.00
CONT_ASSIGN	308	1	1	100.00
CONT_ASSIGN	310	1	1	100.00
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	314	1	1	100.00
CONT_ASSIGN	317	1	1	100.00
CONT_ASSIGN	321	1	1	100.00
CONT_ASSIGN	325	1	1	100.00
CONT_ASSIGN	333	1	1	100.00
CONT_ASSIGN	336	1	1	100.00
CONT_ASSIGN	339	1	1	100.00
CONT_ASSIGN	342	1	1	100.00
CONT_ASSIGN	345	1	1	100.00
CONT_ASSIGN	347	1	1	100.00
CONT_ASSIGN	348	1	1	100.00
CONT_ASSIGN	353	1	1	100.00
CONT_ASSIGN	356	1	1	100.00
CONT_ASSIGN	359	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	364	1	1	100.00
CONT_ASSIGN	368	1	1	100.00
CONT_ASSIGN	370	1	1	100.00
CONT_ASSIGN	371	1	1	100.00
CONT_ASSIGN	374	1	1	100.00
CONT_ASSIGN	393	1	1	100.00
CONT_ASSIGN	396	1	1	100.00
CONT_ASSIGN	400	1	1	100.00
CONT_ASSIGN	409	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
CONT_ASSIGN	411	1	1	100.00
CONT_ASSIGN	412	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	415	1	1	100.00
CONT_ASSIGN	430	1	1	100.00
CONT_ASSIGN	431	1	1	100.00
CONT_ASSIGN	432	1	1	100.00
CONT_ASSIGN	433	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	436	1	1	100.00
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	457	1	1	100.00
CONT_ASSIGN	458	1	1	100.00
CONT_ASSIGN	459	1	1	100.00
CONT_ASSIGN	460	1	1	100.00
CONT_ASSIGN	461	1	1	100.00
CONT_ASSIGN	476	1	1	100.00
CONT_ASSIGN	477	1	1	100.00
CONT_ASSIGN	479	1	1	100.00
CONT_ASSIGN	480	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	483	1	1	100.00
CONT_ASSIGN	485	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	488	1	1	100.00
CONT_ASSIGN	489	1	1	100.00
CONT_ASSIGN	490	1	1	100.00
CONT_ASSIGN	493	1	1	100.00
CONT_ASSIGN	502	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	513	1	1	100.00
CONT_ASSIGN	529	1	1	100.00
CONT_ASSIGN	537	1	1	100.00
CONT_ASSIGN	538	1	1	100.00
CONT_ASSIGN	543	1	1	100.00
CONT_ASSIGN	544	1	1	100.00
CONT_ASSIGN	548	1	1	100.00
CONT_ASSIGN	558	1	1	100.00
CONT_ASSIGN	559	1	1	100.00
CONT_ASSIGN	569	1	1	100.00
CONT_ASSIGN	570	1	1	100.00
CONT_ASSIGN	577	1	1	100.00
CONT_ASSIGN	578	1	1	100.00
CONT_ASSIGN	589	1	1	100.00
CONT_ASSIGN	590	1	1	100.00
CONT_ASSIGN	595	1	1	100.00
CONT_ASSIGN	596	1	1	100.00
CONT_ASSIGN	602	1	1	100.00
CONT_ASSIGN	603	1	1	100.00
CONT_ASSIGN	612	1	1	100.00
CONT_ASSIGN	613	1	1	100.00
CONT_ASSIGN	622	1	1	100.00
CONT_ASSIGN	623	1	1	100.00
CONT_ASSIGN	647	1	1	100.00
CONT_ASSIGN	649	1	1	100.00
CONT_ASSIGN	653	1	1	100.00
CONT_ASSIGN	657	1	1	100.00
CONT_ASSIGN	659	1	1	100.00
CONT_ASSIGN	661	1	1	100.00
CONT_ASSIGN	687	1	1	100.00
CONT_ASSIGN	689	1	1	100.00
CONT_ASSIGN	693	1	1	100.00
CONT_ASSIGN	697	1	1	100.00
CONT_ASSIGN	699	1	1	100.00
CONT_ASSIGN	701	1	1	100.00
CONT_ASSIGN	760	1	1	100.00
CONT_ASSIGN	764	1	1	100.00
CONT_ASSIGN	767	1	1	100.00
CONT_ASSIGN	777	1	1	100.00
CONT_ASSIGN	782	1	1	100.00
CONT_ASSIGN	783	1	1	100.00
CONT_ASSIGN	784	1	1	100.00
CONT_ASSIGN	785	1	1	100.00
CONT_ASSIGN	788	1	1	100.00
CONT_ASSIGN	824	1	1	100.00
CONT_ASSIGN	824	1	1	100.00
CONT_ASSIGN	824	1	1	100.00
CONT_ASSIGN	824	1	1	100.00
CONT_ASSIGN	824	1	1	100.00
CONT_ASSIGN	824	1	1	100.00
CONT_ASSIGN	824	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	851	1	1	100.00
CONT_ASSIGN	852	1	1	100.00
CONT_ASSIGN	853	1	1	100.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	856	1	1	100.00
CONT_ASSIGN	871	1	1	100.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	881	1	1	100.00
CONT_ASSIGN	884	1	1	100.00
CONT_ASSIGN	885	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	910	1	1	100.00
CONT_ASSIGN	910	1	1	100.00
CONT_ASSIGN	910	1	1	100.00
CONT_ASSIGN	910	1	1	100.00
CONT_ASSIGN	910	1	1	100.00
CONT_ASSIGN	910	1	1	100.00
CONT_ASSIGN	910	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	913	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	916	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	919	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	920	1	1	100.00
CONT_ASSIGN	940	1	1	100.00
CONT_ASSIGN	956	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
215	1	1
216	1	1
217	1	1
218	1	1
219	1	1
220	1	1
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
226	1	1
227	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
234	1	1
235	1	1
236	1	1
237	1	1
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
243	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
290	1	1
295	1	1
300	1	1
306	1	1
308	1	1
310	1	1
312	1	1
314	1	1
317	1	1
321	1	1
325	1	1
333	1	1
336	1	1
339	1	1
342	1	1
345	1	1
347	1	1
348	1	1
353	1	1
356	1	1
359	1	1
364	31	31
368	1	1
370	1	1
371	1	1
374	1	1
393	1	1
396	1	1
400	1	1
409	1	1
410	1	1
411	1	1
412	1	1
415	19	19
430	1	1
431	1	1
432	1	1
433	1	1
436	3	3
450	1	1
457	1	1
458	1	1
459	1	1
460	1	1
461	1	1
476	1	1
477	1	1
479	1	1
480	1	1
482	1	1
483	1	1
485	1	1
486	1	1
488	1	1
489	1	1
490	1	1
493	1	1
502	1	1
509	1	1
513	1	1
529	1	1
537	1	1
538	1	1
543	1	1
544	1	1
548	1	1
558	1	1
559	1	1
569	1	1
570	1	1
577	1	1
578	1	1
589	1	1
590	1	1
595	1	1
596	1	1
602	1	1
603	1	1
612	1	1
613	1	1
622	1	1
623	1	1
647	1	1
649	1	1
653	1	1
657	1	1
659	1	1
661	1	1
687	1	1
689	1	1
693	1	1
697	1	1
699	1	1
701	1	1
760	1	1
764	1	1
767	1	1
777	1	1
782	1	1
783	1	1
784	1	1
785	1	1
788	1	1
824	7	7
848	1	1
849	1	1
851	1	1
852	1	1
853	1	1
854	1	1
856	1	1
871	1	1
873	1	1
875	1	1
881	1	1
884	1	1
885	1	1
909	7	7
910	7	7
913	7	7
916	7	7
919	7	7
920	7	7
940	1	1
956	1	1

---

Cond Coverage for Module : edn_core

	Total	Covered	Percent
Conditions	617	555	89.95
Logical	617	555	89.95
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
290-760	91.67
764-956	85.09

---

Branch Coverage for Module : edn_core

	Line No.	Total	Covered	Percent
Branches		104	104	100.00
TERNARY	493	6	6	100.00
TERNARY	502	4	4	100.00
TERNARY	513	7	7	100.00
TERNARY	529	5	5	100.00
TERNARY	548	6	6	100.00
TERNARY	559	6	6	100.00
TERNARY	570	3	3	100.00
TERNARY	578	4	4	100.00
TERNARY	590	3	3	100.00
TERNARY	596	3	3	100.00
TERNARY	603	5	5	100.00
TERNARY	613	5	5	100.00
TERNARY	623	2	2	100.00
TERNARY	649	2	2	100.00
TERNARY	653	2	2	100.00
TERNARY	689	2	2	100.00
TERNARY	693	2	2	100.00
TERNARY	767	6	6	100.00
TERNARY	856	3	3	100.00
TERNARY	873	2	2	100.00
TERNARY	875	3	3	100.00
TERNARY	913	3	3	100.00
TERNARY	913	3	3	100.00
TERNARY	913	3	3	100.00
TERNARY	913	3	3	100.00
TERNARY	913	3	3	100.00
TERNARY	913	3	3	100.00
TERNARY	913	3	3	100.00
IF	215	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv' or '../src/lowrisc_ip_edn_0.1/rtl/edn_core.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	493	((!edn_enable_fo[CsrngCmdReq])) ? 
-2-:	493	(boot_wr_ins_cmd) ? 
-3-:	493	(boot_wr_gen_cmd) ? 
-4-:	493	(boot_wr_uni_cmd) ? 
-5-:	493	(sw_cmd_req_load) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T2,T8,T45
0	0	1	-	-	Covered	T2,T8,T45
0	0	0	1	-	Covered	T2,T8,T27
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	502	((!edn_enable_fo[CsrngCmdReqValid])) ? 
-2-:	502	(cs_cmd_handshake) ? 
-3-:	502	((((sw_cmd_req_load || boot_wr_ins_cmd) || boot_wr_gen_cmd) || boot_wr_uni_cmd)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	513	((!edn_enable_fo[CsrngCmdReqOut])) ? 
-2-:	513	((send_rescmd || capt_rescmd_fifo_cnt)) ? 
-3-:	513	(sfifo_rescmd_pop) ? 
-4-:	513	((send_gencmd || capt_gencmd_fifo_cnt)) ? 
-5-:	513	(sfifo_gencmd_pop) ? 
-6-:	513	((cs_cmd_req_vld_q && (!cs_cmd_handshake))) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	Status	Tests
1	-	-	-	-	-	Covered	T1,T2,T3
0	1	1	-	-	-	Covered	T7,T9,T19
0	1	0	-	-	-	Covered	T7,T9,T19
0	0	-	1	1	-	Covered	T3,T7,T8
0	0	-	1	0	-	Covered	T3,T7,T8
0	0	-	0	-	1	Covered	T1,T2,T3
0	0	-	0	-	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	529	((!edn_enable_fo[CsrngCmdReqValidOut])) ? 
-2-:	529	(cmd_sent) ? 
-3-:	529	((send_rescmd || capt_rescmd_fifo_cnt)) ? 
-4-:	529	((send_gencmd || capt_gencmd_fifo_cnt)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T3,T7,T8
0	0	1	-	Covered	T7,T9,T19
0	0	0	1	Covered	T3,T7,T8
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	548	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	548	((!sw_cmd_valid)) ? 
-3-:	548	(sw_cmd_req_load) ? 
-4-:	548	(accept_sw_cmds_pulse) ? 
-5-:	548	(csrng_cmd_i.csrng_rsp_ack) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T1,T2,T3
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	559	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	559	((!sw_cmd_valid)) ? 
-3-:	559	(sw_cmd_req_load) ? 
-4-:	559	(accept_sw_cmds_pulse) ? 
-5-:	559	(cs_cmd_handshake) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T3
0	0	1	-	-	Covered	T1,T2,T3
0	0	0	1	-	Covered	T1,T2,T3
0	0	0	0	1	Covered	T1,T2,T3
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	570	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	570	((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	578	((!edn_enable_fo[SwCmdSts])) ? 
-2-:	578	(sw_cmd_req_load) ? 
-3-:	578	((csrng_cmd_i.csrng_rsp_ack && sw_cmd_valid)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T2,T3
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	590	((main_sm_done_pulse || (!edn_enable_fo[HwCmdSts]))) ? 
-2-:	590	(boot_wr_ins_cmd) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T8,T45
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	596	((main_sm_done_pulse || (!edn_enable_fo[HwCmdSts]))) ? 
-2-:	596	(auto_req_mode_busy) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T7,T8
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	603	((!edn_enable_fo[HwCmdSts])) ? 
-2-:	603	(sw_cmd_valid) ? 
-3-:	603	((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)) ? 
-4-:	603	((csrng_cmd_i.csrng_rsp_ack && csrng_cmd_i.csrng_rsp_sts)) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T2,T3,T7
0	0	0	1	Covered	T8,T12,T13
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	613	((!edn_enable_fo[HwCmdSts])) ? 
-2-:	613	(sw_cmd_valid) ? 
-3-:	613	((cs_cmd_req_vld_out_q && csrng_cmd_i.csrng_req_ready)) ? 
-4-:	613	(csrng_cmd_i.csrng_rsp_ack) ? 

Branches:

-1-	-2-	-3-	-4-	Status	Tests
1	-	-	-	Covered	T1,T2,T3
0	1	-	-	Covered	T1,T2,T3
0	0	1	-	Covered	T2,T3,T7
0	0	0	1	Covered	T2,T3,T7
0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	623	((((edn_enable_fo[HwCmdSts] && (!sw_cmd_valid)) && cs_cmd_req_vld_out_q) && csrng_cmd_i.csrng_req_ready)) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T7
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	649	(rescmd_handshake) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T9,T19
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	653	(auto_req_mode_busy) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	689	(gencmd_handshake) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	693	(auto_req_mode_busy) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T8
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	767	((!edn_enable_fo[CmdFifoCnt])) ? 
-2-:	767	((cmd_fifo_rst_fo[3] || main_sm_done_pulse)) ? 
-3-:	767	(capt_gencmd_fifo_cnt) ? 
-4-:	767	(capt_rescmd_fifo_cnt) ? 
-5-:	767	((sfifo_gencmd_pop || sfifo_rescmd_pop)) ? 

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T2,T4
0	0	1	-	-	Covered	T3,T7,T8
0	0	0	1	-	Covered	T7,T9,T19
0	0	0	0	1	Covered	T7,T9,T19
0	0	0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	856	((!edn_enable_fo[CsrngFipsEn])) ? 
-2-:	856	((packer_cs_push && packer_cs_wready)) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	873	(cs_rdata_capt_vld) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	875	((!edn_enable_fo[CsrngDataVld])) ? 
-2-:	875	(cs_rdata_capt_vld) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	913	(packer_ep_clr[0]) ? 
-2-:	913	((packer_ep_push[0] && packer_ep_wready[0])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T7
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	913	(packer_ep_clr[1]) ? 
-2-:	913	((packer_ep_push[1] && packer_ep_wready[1])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T3,T19,T20
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	913	(packer_ep_clr[2]) ? 
-2-:	913	((packer_ep_push[2] && packer_ep_wready[2])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T21,T20,T22
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	913	(packer_ep_clr[3]) ? 
-2-:	913	((packer_ep_push[3] && packer_ep_wready[3])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T19,T24,T31
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	913	(packer_ep_clr[4]) ? 
-2-:	913	((packer_ep_push[4] && packer_ep_wready[4])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T9,T19
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	913	(packer_ep_clr[5]) ? 
-2-:	913	((packer_ep_push[5] && packer_ep_wready[5])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T25,T33
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	913	(packer_ep_clr[6]) ? 
-2-:	913	((packer_ep_push[6] && packer_ep_wready[6])) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T2,T9,T19
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	215	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : edn_core

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CsErrAcceptNoEntropy_A	214905362	6777	0	0
CsErrIssueNoCommands_A	214905362	6777	0	0

CsErrAcceptNoEntropy_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214905362	6777	0	0
T5	1206	0	0	0
T8	2215	155	0	0
T9	2296	0	0	0
T12	0	129	0	0
T13	0	130	0	0
T19	7573	0	0	0
T23	369	0	0	0
T25	2090	0	0	0
T27	3334	0	0	0
T39	0	129	0	0
T40	0	117	0	0
T43	1153	0	0	0
T44	1840	0	0	0
T45	1200	0	0	0
T99	0	129	0	0
T151	0	145	0	0
T154	0	151	0	0
T161	0	117	0	0
T162	0	140	0	0

CsErrIssueNoCommands_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	214905362	6777	0	0
T5	1206	0	0	0
T8	2215	155	0	0
T9	2296	0	0	0
T12	0	129	0	0
T13	0	130	0	0
T19	7573	0	0	0
T23	369	0	0	0
T25	2090	0	0	0
T27	3334	0	0	0
T39	0	129	0	0
T40	0	117	0	0
T43	1153	0	0	0
T44	1840	0	0	0
T45	1200	0	0	0
T99	0	129	0	0
T151	0	145	0	0
T154	0	151	0	0
T161	0	117	0	0
T162	0	140	0	0