Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.29	98.27	93.71	96.79	80.35	96.87	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	90.30	99.92	92.29	70.79	80.35	99.55	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T21,T22,T23

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T93,T94,T95
1	0	Covered	T4,T5,T18

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1170	1170	100.00
Total Bits 0->1	585	585	100.00
Total Bits 1->0	585	585	100.00

Ports	69	69	100.00
Port Bits	1170	1170	100.00
Port Bits 0->1	585	585	100.00
Port Bits 1->0	585	585	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T17,T19,T9	Yes	T17,T19,T9	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
tl_i.a_address[31:0]	Yes	Yes	T6,T16,T17	Yes	T6,T16,T17	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T109,T110,T111	Yes	T109,T110,T111	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T4,T5	Yes	T1,T3,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T5,T6	Yes	T3,T5,T6	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T3,T17	Yes	T1,T3,T17	INPUT
edn_i[2].edn_req	Yes	Yes	T4,T16,T17	Yes	T4,T16,T17	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T16,T19	Yes	T3,T16,T19	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T112,T103	Yes	T3,T112,T103	INPUT
edn_i[5].edn_req	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	INPUT
edn_i[6].edn_req	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T6,T16,T99	Yes	T3,T6,T16	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T6,T16,T18	Yes	T3,T6,T16	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T6,T16	Yes	T3,T6,T16	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T3,T10,T24	Yes	T1,T3,T10	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T3,T113,T11	Yes	T3,T17,T24	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T3,T17	Yes	T1,T3,T17	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T16,T17,T24	Yes	T16,T17,T24	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T16,T17,T24	Yes	T16,T17,T24	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T16,T17,T24	Yes	T16,T17,T24	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T16,T19	Yes	T3,T16,T19	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T3,T16,T10	Yes	T3,T16,T10	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T16,T19	Yes	T3,T16,T19	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T112,T103	Yes	T3,T112,T103	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T112,T103,T114	Yes	T112,T103,T114	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T112,T103	Yes	T3,T112,T103	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T2,T3,T10	Yes	T2,T3,T10	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T115,T114,T11	Yes	T1,T115,T114	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T1,T3,T9	Yes	T1,T3,T9	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T3,T6	Yes	T3,T6,T16	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T3,T6	Yes	T1,T3,T6	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[1:0]	Yes	Yes	T21,T22,T23	Yes	T21,T22,T23	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T116,T117,T21	Yes	T116,T117,T21	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T116,T117,T21	Yes	T116,T117,T21	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T5,T18	Yes	T4,T5,T18	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T6,T99,T109	Yes	T6,T99,T109	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T6,T18,T19	Yes	T6,T18,T19	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	43	43	100.00	43	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	43	43	100.00	43	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	212405120	212250097	0	0
CsrngAppIfOut_A	212405120	212250097	0	0
FpvSecCmCntAlertCheck_A	212405120	116	0	0
FpvSecCmMainFsmCheck_A	212405120	80	0	0
FpvSecCmRegWeOnehotCheck_A	212405120	80	0	0
IntrEdnCmdReqDoneKnownO_A	212405120	212250097	0	0
TlAReadyKnownO_A	212405120	212250097	0	0
TlDValidKnownO_A	212405120	212250097	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	212405120	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	212405120	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	212405120	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	212405120	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	212405120	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	212405120	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	212405120	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	212405120	490533	0	302
gen_edn_if_asserts[0].EdnDataStable_A	212405120	31092	0	353
gen_edn_if_asserts[0].EdnEndPointOut_A	212405120	212250097	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	212405120	137193	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	212405120	490533	0	302
gen_edn_if_asserts[1].EdnDataStable_A	212405120	3216	0	108
gen_edn_if_asserts[1].EdnEndPointOut_A	212405120	212250097	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	212405120	137193	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	212405120	490533	0	302
gen_edn_if_asserts[2].EdnDataStable_A	212405120	5771	0	104
gen_edn_if_asserts[2].EdnEndPointOut_A	212405120	212250097	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	212405120	137193	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	212405120	490533	0	302
gen_edn_if_asserts[3].EdnDataStable_A	212405120	3513	0	100
gen_edn_if_asserts[3].EdnEndPointOut_A	212405120	212250097	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	212405120	137193	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	212405120	490533	0	302
gen_edn_if_asserts[4].EdnDataStable_A	212405120	3702	0	83
gen_edn_if_asserts[4].EdnEndPointOut_A	212405120	212250097	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	212405120	137193	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	212405120	490533	0	302
gen_edn_if_asserts[5].EdnDataStable_A	212405120	4489	0	75
gen_edn_if_asserts[5].EdnEndPointOut_A	212405120	212250097	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	212405120	137193	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	212405120	490533	0	302
gen_edn_if_asserts[6].EdnDataStable_A	212405120	3660	0	63
gen_edn_if_asserts[6].EdnEndPointOut_A	212405120	212250097	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	212405120	137193	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	116	0	0
T7	1283	0	0	0
T13	995	1	0	0
T14	0	1	0	0
T15	0	1	0	0
T20	753	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T61	0	1	0	0
T93	0	10	0	0
T94	0	20	0	0
T96	1792	0	0	0
T103	681	0	0	0
T112	1860	0	0	0
T114	2695	0	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	1477	0	0	0
T121	18289	0	0	0
T122	16130	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	80	0	0
T77	1078	0	0	0
T85	1256	0	0	0
T87	1967	0	0	0
T90	2299	0	0	0
T93	18035	10	0	0
T94	0	20	0	0
T95	0	20	0	0
T123	0	10	0	0
T124	0	20	0	0
T125	4453	0	0	0
T126	1304	0	0	0
T127	27747	0	0	0
T128	735837	0	0	0
T129	1094	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	80	0	0
T77	1078	0	0	0
T85	1256	0	0	0
T87	1967	0	0	0
T90	2299	0	0	0
T93	18035	10	0	0
T94	0	20	0	0
T95	0	20	0	0
T123	0	10	0	0
T124	0	20	0	0
T125	4453	0	0	0
T126	1304	0	0	0
T127	27747	0	0	0
T128	735837	0	0	0
T129	1094	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	80	0	0
T77	1078	0	0	0
T85	1256	0	0	0
T87	1967	0	0	0
T90	2299	0	0	0
T93	18035	10	0	0
T94	0	20	0	0
T95	0	20	0	0
T123	0	10	0	0
T124	0	20	0	0
T125	4453	0	0	0
T126	1304	0	0	0
T127	27747	0	0	0
T128	735837	0	0	0
T129	1094	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	80	0	0
T77	1078	0	0	0
T85	1256	0	0	0
T87	1967	0	0	0
T90	2299	0	0	0
T93	18035	10	0	0
T94	0	20	0	0
T95	0	20	0	0
T123	0	10	0	0
T124	0	20	0	0
T125	4453	0	0	0
T126	1304	0	0	0
T127	27747	0	0	0
T128	735837	0	0	0
T129	1094	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	80	0	0
T77	1078	0	0	0
T85	1256	0	0	0
T87	1967	0	0	0
T90	2299	0	0	0
T93	18035	10	0	0
T94	0	20	0	0
T95	0	20	0	0
T123	0	10	0	0
T124	0	20	0	0
T125	4453	0	0	0
T126	1304	0	0	0
T127	27747	0	0	0
T128	735837	0	0	0
T129	1094	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	80	0	0
T77	1078	0	0	0
T85	1256	0	0	0
T87	1967	0	0	0
T90	2299	0	0	0
T93	18035	10	0	0
T94	0	20	0	0
T95	0	20	0	0
T123	0	10	0	0
T124	0	20	0	0
T125	4453	0	0	0
T126	1304	0	0	0
T127	27747	0	0	0
T128	735837	0	0	0
T129	1094	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	80	0	0
T77	1078	0	0	0
T85	1256	0	0	0
T87	1967	0	0	0
T90	2299	0	0	0
T93	18035	10	0	0
T94	0	20	0	0
T95	0	20	0	0
T123	0	10	0	0
T124	0	20	0	0
T125	4453	0	0	0
T126	1304	0	0	0
T127	27747	0	0	0
T128	735837	0	0	0
T129	1094	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	80	0	0
T77	1078	0	0	0
T85	1256	0	0	0
T87	1967	0	0	0
T90	2299	0	0	0
T93	18035	10	0	0
T94	0	20	0	0
T95	0	20	0	0
T123	0	10	0	0
T124	0	20	0	0
T125	4453	0	0	0
T126	1304	0	0	0
T127	27747	0	0	0
T128	735837	0	0	0
T129	1094	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	80	0	0
T77	1078	0	0	0
T85	1256	0	0	0
T87	1967	0	0	0
T90	2299	0	0	0
T93	18035	10	0	0
T94	0	20	0	0
T95	0	20	0	0
T123	0	10	0	0
T124	0	20	0	0
T125	4453	0	0	0
T126	1304	0	0	0
T127	27747	0	0	0
T128	735837	0	0	0
T129	1094	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	490533	0	302
T1	4034	977	0	2
T2	1112	80	0	0
T3	1935	16	0	0
T4	886	399	0	0
T5	1563	923	0	0
T6	13174	98	0	0
T9	0	0	0	2
T16	2516	27	0	0
T17	3799	95	0	0
T18	647	188	0	0
T19	2143	1104	0	0
T26	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T56	0	0	0	2
T109	0	0	0	2
T111	0	0	0	2
T116	0	0	0	2
T117	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	31092	0	353
T3	1935	3	0	1
T4	886	0	0	0
T5	1563	0	0	0
T6	13174	17	0	1
T9	2832	0	0	0
T10	2906	0	0	0
T16	2516	49	0	1
T17	3799	0	0	0
T18	647	1	0	0
T19	2143	0	0	0
T25	0	7	0	1
T99	0	23	0	1
T100	0	3	0	1
T106	0	1	0	0
T109	0	64	0	0
T110	0	0	0	1
T120	0	0	0	1
T121	0	0	0	1
T130	0	18	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	137193	0	0
T4	886	415	0	0
T5	1563	892	0	0
T6	13174	0	0	0
T7	0	409	0	0
T9	2832	0	0	0
T10	2906	0	0	0
T13	0	379	0	0
T16	2516	0	0	0
T17	3799	0	0	0
T18	647	22	0	0
T19	2143	20	0	0
T59	0	1112	0	0
T96	0	883	0	0
T99	11365	0	0	0
T103	0	7	0	0
T106	0	7	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	490533	0	302
T1	4034	977	0	2
T2	1112	80	0	0
T3	1935	16	0	0
T4	886	399	0	0
T5	1563	923	0	0
T6	13174	98	0	0
T9	0	0	0	2
T16	2516	27	0	0
T17	3799	95	0	0
T18	647	188	0	0
T19	2143	1104	0	0
T26	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T56	0	0	0	2
T109	0	0	0	2
T111	0	0	0	2
T116	0	0	0	2
T117	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	3216	0	108
T1	4034	1	0	0
T2	1112	0	0	0
T3	1935	37	0	1
T4	886	0	0	0
T5	1563	0	0	0
T6	13174	0	0	0
T10	0	3	0	1
T11	0	0	0	1
T16	2516	0	0	0
T17	3799	3	0	1
T18	647	0	0	0
T19	2143	0	0	0
T24	0	3	0	1
T38	0	3	0	1
T112	0	3	0	1
T113	0	32	0	1
T114	0	3	0	1
T115	0	3	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	137193	0	0
T4	886	415	0	0
T5	1563	892	0	0
T6	13174	0	0	0
T7	0	409	0	0
T9	2832	0	0	0
T10	2906	0	0	0
T13	0	379	0	0
T16	2516	0	0	0
T17	3799	0	0	0
T18	647	22	0	0
T19	2143	20	0	0
T59	0	1112	0	0
T96	0	883	0	0
T99	11365	0	0	0
T103	0	7	0	0
T106	0	7	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	490533	0	302
T1	4034	977	0	2
T2	1112	80	0	0
T3	1935	16	0	0
T4	886	399	0	0
T5	1563	923	0	0
T6	13174	98	0	0
T9	0	0	0	2
T16	2516	27	0	0
T17	3799	95	0	0
T18	647	188	0	0
T19	2143	1104	0	0
T26	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T56	0	0	0	2
T109	0	0	0	2
T111	0	0	0	2
T116	0	0	0	2
T117	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	5771	0	104
T9	2832	0	0	0
T10	2906	0	0	0
T11	0	7	0	1
T16	2516	43	0	1
T17	3799	16	0	1
T18	647	0	0	0
T19	2143	0	0	0
T22	0	0	0	1
T24	4197	49	0	1
T26	0	4	0	0
T99	11365	0	0	0
T113	0	56	0	1
T114	0	40	0	1
T115	2044	0	0	0
T130	2501	0	0	0
T131	0	3	0	1
T132	0	3	0	1
T133	0	51	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	137193	0	0
T4	886	415	0	0
T5	1563	892	0	0
T6	13174	0	0	0
T7	0	409	0	0
T9	2832	0	0	0
T10	2906	0	0	0
T13	0	379	0	0
T16	2516	0	0	0
T17	3799	0	0	0
T18	647	22	0	0
T19	2143	20	0	0
T59	0	1112	0	0
T96	0	883	0	0
T99	11365	0	0	0
T103	0	7	0	0
T106	0	7	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	490533	0	302
T1	4034	977	0	2
T2	1112	80	0	0
T3	1935	16	0	0
T4	886	399	0	0
T5	1563	923	0	0
T6	13174	98	0	0
T9	0	0	0	2
T16	2516	27	0	0
T17	3799	95	0	0
T18	647	188	0	0
T19	2143	1104	0	0
T26	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T56	0	0	0	2
T109	0	0	0	2
T111	0	0	0	2
T116	0	0	0	2
T117	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	3513	0	100
T3	1935	21	0	1
T4	886	0	0	0
T5	1563	0	0	0
T6	13174	0	0	0
T9	2832	0	0	0
T10	2906	15	0	1
T11	0	54	0	1
T16	2516	53	0	1
T17	3799	0	0	0
T18	647	0	0	0
T19	2143	1	0	0
T26	0	4	0	0
T104	0	1	0	0
T113	0	3	0	1
T114	0	3	0	1
T133	0	0	0	1
T134	0	55	0	1
T135	0	0	0	1
T136	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	137193	0	0
T4	886	415	0	0
T5	1563	892	0	0
T6	13174	0	0	0
T7	0	409	0	0
T9	2832	0	0	0
T10	2906	0	0	0
T13	0	379	0	0
T16	2516	0	0	0
T17	3799	0	0	0
T18	647	22	0	0
T19	2143	20	0	0
T59	0	1112	0	0
T96	0	883	0	0
T99	11365	0	0	0
T103	0	7	0	0
T106	0	7	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	490533	0	302
T1	4034	977	0	2
T2	1112	80	0	0
T3	1935	16	0	0
T4	886	399	0	0
T5	1563	923	0	0
T6	13174	98	0	0
T9	0	0	0	2
T16	2516	27	0	0
T17	3799	95	0	0
T18	647	188	0	0
T19	2143	1104	0	0
T26	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T56	0	0	0	2
T109	0	0	0	2
T111	0	0	0	2
T116	0	0	0	2
T117	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	3702	0	83
T3	1935	3	0	1
T4	886	0	0	0
T5	1563	0	0	0
T6	13174	0	0	0
T9	2832	0	0	0
T10	2906	0	0	0
T11	0	3	0	1
T16	2516	0	0	0
T17	3799	0	0	0
T18	647	0	0	0
T19	2143	0	0	0
T103	0	1	0	0
T112	0	15	0	1
T114	0	25	0	1
T133	0	68	0	1
T136	0	3	0	1
T137	0	58	0	1
T138	0	16	0	1
T139	0	4	0	0
T140	0	0	0	1
T141	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	137193	0	0
T4	886	415	0	0
T5	1563	892	0	0
T6	13174	0	0	0
T7	0	409	0	0
T9	2832	0	0	0
T10	2906	0	0	0
T13	0	379	0	0
T16	2516	0	0	0
T17	3799	0	0	0
T18	647	22	0	0
T19	2143	20	0	0
T59	0	1112	0	0
T96	0	883	0	0
T99	11365	0	0	0
T103	0	7	0	0
T106	0	7	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	490533	0	302
T1	4034	977	0	2
T2	1112	80	0	0
T3	1935	16	0	0
T4	886	399	0	0
T5	1563	923	0	0
T6	13174	98	0	0
T9	0	0	0	2
T16	2516	27	0	0
T17	3799	95	0	0
T18	647	188	0	0
T19	2143	1104	0	0
T26	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T56	0	0	0	2
T109	0	0	0	2
T111	0	0	0	2
T116	0	0	0	2
T117	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	4489	0	75
T2	1112	4	0	0
T3	1935	30	0	1
T4	886	0	0	0
T5	1563	0	0	0
T6	13174	0	0	0
T9	2832	0	0	0
T10	0	58	0	1
T11	0	42	0	1
T16	2516	0	0	0
T17	3799	0	0	0
T18	647	0	0	0
T19	2143	0	0	0
T24	0	3	0	1
T98	0	1	0	0
T113	0	3	0	1
T114	0	61	0	1
T133	0	3	0	1
T136	0	56	0	1
T140	0	0	0	1
T142	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	137193	0	0
T4	886	415	0	0
T5	1563	892	0	0
T6	13174	0	0	0
T7	0	409	0	0
T9	2832	0	0	0
T10	2906	0	0	0
T13	0	379	0	0
T16	2516	0	0	0
T17	3799	0	0	0
T18	647	22	0	0
T19	2143	20	0	0
T59	0	1112	0	0
T96	0	883	0	0
T99	11365	0	0	0
T103	0	7	0	0
T106	0	7	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	490533	0	302
T1	4034	977	0	2
T2	1112	80	0	0
T3	1935	16	0	0
T4	886	399	0	0
T5	1563	923	0	0
T6	13174	98	0	0
T9	0	0	0	2
T16	2516	27	0	0
T17	3799	95	0	0
T18	647	188	0	0
T19	2143	1104	0	0
T26	0	0	0	2
T42	0	0	0	2
T43	0	0	0	2
T56	0	0	0	2
T109	0	0	0	2
T111	0	0	0	2
T116	0	0	0	2
T117	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	3660	0	63
T1	4034	4	0	0
T2	1112	0	0	0
T3	1935	6	0	1
T4	886	0	0	0
T5	1563	0	0	0
T6	13174	0	0	0
T9	0	4	0	0
T11	0	26	0	1
T16	2516	0	0	0
T17	3799	0	0	0
T18	647	0	0	0
T19	2143	0	0	0
T20	0	3	0	1
T113	0	3	0	1
T114	0	19	0	1
T115	0	13	0	1
T133	0	3	0	1
T136	0	0	0	1
T142	0	0	0	1
T143	0	39	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	212250097	0	0
T1	4034	3960	0	0
T2	1112	1030	0	0
T3	1935	1865	0	0
T4	886	737	0	0
T5	1563	1425	0	0
T6	13174	12811	0	0
T16	2516	2446	0	0
T17	3799	3733	0	0
T18	647	500	0	0
T19	2143	2005	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212405120	137193	0	0
T4	886	415	0	0
T5	1563	892	0	0
T6	13174	0	0	0
T7	0	409	0	0
T9	2832	0	0	0
T10	2906	0	0	0
T13	0	379	0	0
T16	2516	0	0	0
T17	3799	0	0	0
T18	647	22	0	0
T19	2143	20	0	0
T59	0	1112	0	0
T96	0	883	0	0
T99	11365	0	0	0
T103	0	7	0	0
T106	0	7	0	0