Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	212957964	9745058	0	0
boot_gen_cmd_rd_A	212957964	27633	0	0
boot_ins_cmd_rd_A	212957964	32512	0	0
ctrl_rd_A	212957964	28142	0	0
err_code_test_rd_A	212957964	31967	0	0
intr_enable_rd_A	212957964	32275	0	0
max_num_reqs_between_reseeds_rd_A	212957964	28521	0	0
regwen_rd_A	212957964	31805	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212957964	9745058	0	0
T7	1283	0	0	0
T13	995	0	0	0
T103	681	0	0	0
T109	167038	60869	0	0
T110	510651	293895	0	0
T111	0	160865	0	0
T112	1860	0	0	0
T114	2695	0	0	0
T120	1477	0	0	0
T121	18289	0	0	0
T150	7609	0	0	0
T181	0	189592	0	0
T182	0	245509	0	0
T183	0	280223	0	0
T184	0	379840	0	0
T185	0	314487	0	0
T186	0	15575	0	0
T187	0	388522	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212957964	27633	0	0
T7	1283	0	0	0
T13	995	0	0	0
T103	681	0	0	0
T109	167038	879	0	0
T110	510651	0	0	0
T112	1860	0	0	0
T114	2695	0	0	0
T120	1477	0	0	0
T121	18289	0	0	0
T150	7609	0	0	0
T181	0	2983	0	0
T186	0	477	0	0
T188	0	4335	0	0
T189	0	601	0	0
T190	0	3402	0	0
T191	0	3056	0	0
T192	0	675	0	0
T193	0	907	0	0
T194	0	758	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212957964	32512	0	0
T7	1283	0	0	0
T13	995	0	0	0
T103	681	0	0	0
T109	167038	1188	0	0
T110	510651	0	0	0
T112	1860	0	0	0
T114	2695	0	0	0
T120	1477	0	0	0
T121	18289	0	0	0
T150	7609	0	0	0
T181	0	3426	0	0
T186	0	492	0	0
T188	0	5249	0	0
T189	0	667	0	0
T190	0	3837	0	0
T191	0	3702	0	0
T192	0	808	0	0
T193	0	1257	0	0
T194	0	1052	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212957964	28142	0	0
T7	1283	0	0	0
T13	995	0	0	0
T102	0	8	0	0
T103	681	0	0	0
T109	167038	1022	0	0
T110	510651	0	0	0
T112	1860	0	0	0
T114	2695	0	0	0
T119	0	9	0	0
T120	1477	0	0	0
T121	18289	0	0	0
T150	7609	0	0	0
T181	0	3045	0	0
T186	0	558	0	0
T188	0	4438	0	0
T195	0	1	0	0
T196	0	3	0	0
T197	0	5	0	0
T198	0	3	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212957964	31967	0	0
T7	1283	0	0	0
T13	995	0	0	0
T103	681	0	0	0
T109	167038	957	0	0
T110	510651	0	0	0
T112	1860	0	0	0
T114	2695	0	0	0
T120	1477	0	0	0
T121	18289	0	0	0
T150	7609	0	0	0
T181	0	3385	0	0
T186	0	514	0	0
T188	0	5020	0	0
T189	0	533	0	0
T190	0	4015	0	0
T191	0	3769	0	0
T192	0	761	0	0
T193	0	1207	0	0
T194	0	1103	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212957964	32275	0	0
T7	1283	0	0	0
T13	995	0	0	0
T103	681	0	0	0
T109	167038	1227	0	0
T110	510651	0	0	0
T112	1860	0	0	0
T114	2695	0	0	0
T120	1477	0	0	0
T121	18289	0	0	0
T149	0	14	0	0
T150	7609	0	0	0
T181	0	3149	0	0
T186	0	606	0	0
T188	0	5033	0	0
T189	0	584	0	0
T190	0	3948	0	0
T196	0	74	0	0
T199	0	91	0	0
T200	0	12	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212957964	28521	0	0
T7	1283	0	0	0
T13	995	0	0	0
T103	681	0	0	0
T109	167038	913	0	0
T110	510651	0	0	0
T112	1860	0	0	0
T114	2695	0	0	0
T120	1477	0	0	0
T121	18289	0	0	0
T150	7609	0	0	0
T181	0	3051	0	0
T186	0	437	0	0
T188	0	4443	0	0
T189	0	502	0	0
T190	0	3273	0	0
T191	0	3231	0	0
T192	0	754	0	0
T193	0	1083	0	0
T194	0	807	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	212957964	31805	0	0
T7	1283	0	0	0
T13	995	0	0	0
T103	681	0	0	0
T109	167038	1045	0	0
T110	510651	0	0	0
T112	1860	0	0	0
T114	2695	0	0	0
T120	1477	0	0	0
T121	18289	0	0	0
T150	7609	0	0	0
T181	0	3413	0	0
T186	0	431	0	0
T188	0	4965	0	0
T189	0	648	0	0
T190	0	3935	0	0
T191	0	3571	0	0
T192	0	719	0	0
T193	0	1121	0	0
T194	0	923	0	0