Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.42	98.24	93.82	97.01	80.92	96.76	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.38	99.92	92.48	82.54	80.92	99.52	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T31,T32,T33

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T4,T6,T39

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1170	1170	100.00
Total Bits 0->1	585	585	100.00
Total Bits 1->0	585	585	100.00

Ports	69	69	100.00
Port Bits	1170	1170	100.00
Port Bits 0->1	585	585	100.00
Port Bits 1->0	585	585	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T2,T3,T7	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T24,T26,T27	Yes	T24,T26,T27	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T7	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T7	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T3,T24	Yes	T1,T3,T7	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T3,T7	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T3,T7	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T42,T43,T44	Yes	T42,T43,T44	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T7	Yes	T1,T3,T7	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T3,T7	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T7	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T3,T7,T24	Yes	T3,T7,T24	INPUT
edn_i[1].edn_req	Yes	Yes	T24,T45,T46	Yes	T24,T45,T46	INPUT
edn_i[2].edn_req	Yes	Yes	T24,T47,T48	Yes	T24,T47,T48	INPUT
edn_i[3].edn_req	Yes	Yes	T1,T24,T27	Yes	T1,T24,T27	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T27,T49	Yes	T2,T27,T49	INPUT
edn_i[5].edn_req	Yes	Yes	T27,T47,T46	Yes	T27,T47,T46	INPUT
edn_i[6].edn_req	Yes	Yes	T27,T39,T46	Yes	T27,T39,T46	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T3,T7,T24	Yes	T3,T7,T24	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T7,T24	Yes	T3,T7,T24	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T3,T7,T24	Yes	T3,T7,T24	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T24,T45,T46	Yes	T24,T45,T46	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T45,T50,T9	Yes	T45,T50,T51	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T24,T45,T46	Yes	T24,T45,T46	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T24,T47,T48	Yes	T24,T47,T48	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T48,T52,T53	Yes	T24,T48,T52	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T24,T47,T48	Yes	T24,T47,T48	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T1,T24,T27	Yes	T1,T24,T27	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T24,T27,T32	Yes	T24,T27,T48	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T1,T24,T27	Yes	T1,T24,T27	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T2,T27,T49	Yes	T2,T27,T49	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T34,T54,T55	Yes	T2,T52,T34	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T2,T27,T49	Yes	T2,T27,T49	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T27,T47,T46	Yes	T27,T47,T46	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T47,T46,T51	Yes	T47,T46,T51	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T27,T47,T46	Yes	T27,T47,T46	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T46,T51,T56	Yes	T27,T46,T51	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T39,T46,T51	Yes	T27,T39,T46	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T27,T39,T46	Yes	T27,T39,T46	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T7	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T7,T24	Yes	T3,T7,T24	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T7,T24	Yes	T3,T7,T24	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[1:0]	Yes	Yes	T31,T33,T57	Yes	T31,T33,T57	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T26,T58,T59	Yes	T26,T58,T59	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T4,T26,T6	Yes	T4,T26,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T26,T58,T59	Yes	T26,T58,T59	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T4,T26,T6	Yes	T4,T26,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T42,T43	Yes	T5,T42,T43	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T39,T42,T43	Yes	T39,T42,T43	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	252892838	252716756	0	0
CsrngAppIfOut_A	252892838	252716756	0	0
FpvSecCmCntAlertCheck_A	252892838	135	0	0
FpvSecCmGenCmdFifoRptrCheck_A	252892838	80	0	0
FpvSecCmGenCmdFifoWptrCheck_A	252892838	80	0	0
FpvSecCmMainFsmCheck_A	252892838	80	0	0
FpvSecCmRegWeOnehotCheck_A	252892838	80	0	0
FpvSecCmResCmdFifoRptrCheck_A	252892838	80	0	0
FpvSecCmResCmdFifoWptrCheck_A	252892838	80	0	0
IntrEdnCmdReqDoneKnownO_A	252892838	252716756	0	0
TlAReadyKnownO_A	252892838	252716756	0	0
TlDValidKnownO_A	252892838	252716756	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	252892838	80	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	252892838	80	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	252892838	80	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	252892838	80	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	252892838	80	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	252892838	80	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	252892838	80	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	252892838	517383	0	292
gen_edn_if_asserts[0].EdnDataStable_A	252892838	24192	0	349
gen_edn_if_asserts[0].EdnEndPointOut_A	252892838	252716756	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	252892838	149212	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	252892838	517383	0	292
gen_edn_if_asserts[1].EdnDataStable_A	252892838	4865	0	117
gen_edn_if_asserts[1].EdnEndPointOut_A	252892838	252716756	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	252892838	149212	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	252892838	517383	0	292
gen_edn_if_asserts[2].EdnDataStable_A	252892838	54111	0	103
gen_edn_if_asserts[2].EdnEndPointOut_A	252892838	252716756	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	252892838	149212	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	252892838	517383	0	292
gen_edn_if_asserts[3].EdnDataStable_A	252892838	3522	0	107
gen_edn_if_asserts[3].EdnEndPointOut_A	252892838	252716756	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	252892838	149212	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	252892838	517383	0	292
gen_edn_if_asserts[4].EdnDataStable_A	252892838	2301	0	100
gen_edn_if_asserts[4].EdnEndPointOut_A	252892838	252716756	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	252892838	149212	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	252892838	517383	0	292
gen_edn_if_asserts[5].EdnDataStable_A	252892838	4935	0	97
gen_edn_if_asserts[5].EdnEndPointOut_A	252892838	252716756	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	252892838	149212	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	252892838	517383	0	292
gen_edn_if_asserts[6].EdnDataStable_A	252892838	5742	0	93
gen_edn_if_asserts[6].EdnEndPointOut_A	252892838	252716756	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	252892838	149212	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	135	0	0
T4	1007	1	0	0
T5	16117	0	0	0
T6	798	0	0	0
T9	0	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T39	864	0	0	0
T42	809743	0	0	0
T58	2374	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	80	0	0
T12	2289	0	0	0
T17	23083	10	0	0
T18	0	20	0	0
T19	0	20	0	0
T66	0	20	0	0
T67	0	10	0	0
T68	3240	0	0	0
T69	970	0	0	0
T70	2023	0	0	0
T71	890	0	0	0
T72	4490	0	0	0
T73	2052	0	0	0
T74	355821	0	0	0
T75	1286	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	517383	0	292
T1	2911	288	0	0
T2	1241	35	0	0
T3	5722	27	0	0
T4	1007	629	0	0
T5	16117	909	0	0
T7	5330	205	0	0
T10	0	0	0	2
T14	0	0	0	2
T24	1964	19	0	0
T25	2435	14	0	0
T26	1669	1567	0	2
T27	4597	33	0	0
T42	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	24192	0	349
T3	5722	21	0	1
T4	1007	0	0	0
T5	16117	6	0	1
T6	798	0	0	0
T7	5330	653	0	1
T24	1964	40	0	1
T25	2435	39	0	1
T26	1669	0	0	0
T27	4597	3	0	1
T28	1076	3	0	1
T42	0	87	0	0
T43	0	44	0	0
T46	0	3	0	1
T52	0	0	0	1
T78	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	149212	0	0
T4	1007	313	0	0
T5	16117	0	0	0
T6	798	362	0	0
T8	0	1098	0	0
T15	0	1113	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T39	864	386	0	0
T42	809743	0	0	0
T58	2374	0	0	0
T79	0	1110	0	0
T80	0	1149	0	0
T81	0	1090	0	0
T82	0	1143	0	0
T83	0	281	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	517383	0	292
T1	2911	288	0	0
T2	1241	35	0	0
T3	5722	27	0	0
T4	1007	629	0	0
T5	16117	909	0	0
T7	5330	205	0	0
T10	0	0	0	2
T14	0	0	0	2
T24	1964	19	0	0
T25	2435	14	0	0
T26	1669	1567	0	2
T27	4597	33	0	0
T42	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	4865	0	117
T4	1007	0	0	0
T5	16117	0	0	0
T6	798	0	0	0
T24	1964	3	0	1
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T33	0	4	0	1
T39	864	0	0	0
T42	809743	0	0	0
T45	0	4	0	0
T46	0	3	0	1
T50	0	4	0	0
T51	0	3	0	1
T52	0	20	0	1
T54	0	3	0	1
T84	0	3	0	1
T85	0	4	0	0
T86	0	0	0	1
T87	0	0	0	1
T88	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	149212	0	0
T4	1007	313	0	0
T5	16117	0	0	0
T6	798	362	0	0
T8	0	1098	0	0
T15	0	1113	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T39	864	386	0	0
T42	809743	0	0	0
T58	2374	0	0	0
T79	0	1110	0	0
T80	0	1149	0	0
T81	0	1090	0	0
T82	0	1143	0	0
T83	0	281	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	517383	0	292
T1	2911	288	0	0
T2	1241	35	0	0
T3	5722	27	0	0
T4	1007	629	0	0
T5	16117	909	0	0
T7	5330	205	0	0
T10	0	0	0	2
T14	0	0	0	2
T24	1964	19	0	0
T25	2435	14	0	0
T26	1669	1567	0	2
T27	4597	33	0	0
T42	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	54111	0	103
T4	1007	0	0	0
T5	16117	0	0	0
T6	798	0	0	0
T14	0	5	0	0
T23	0	1	0	0
T24	1964	3	0	1
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T32	0	4	0	1
T39	864	0	0	0
T42	809743	0	0	0
T47	0	3	0	1
T48	0	10	0	1
T52	0	4	0	1
T53	0	63	0	1
T54	0	3	0	1
T88	0	0	0	1
T89	0	3	0	1
T90	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	149212	0	0
T4	1007	313	0	0
T5	16117	0	0	0
T6	798	362	0	0
T8	0	1098	0	0
T15	0	1113	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T39	864	386	0	0
T42	809743	0	0	0
T58	2374	0	0	0
T79	0	1110	0	0
T80	0	1149	0	0
T81	0	1090	0	0
T82	0	1143	0	0
T83	0	281	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	517383	0	292
T1	2911	288	0	0
T2	1241	35	0	0
T3	5722	27	0	0
T4	1007	629	0	0
T5	16117	909	0	0
T7	5330	205	0	0
T10	0	0	0	2
T14	0	0	0	2
T24	1964	19	0	0
T25	2435	14	0	0
T26	1669	1567	0	2
T27	4597	33	0	0
T42	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	3522	0	107
T1	2911	3	0	1
T2	1241	0	0	0
T3	5722	0	0	0
T4	1007	0	0	0
T5	16117	0	0	0
T7	5330	0	0	0
T24	1964	58	0	1
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	29	0	1
T32	0	4	0	0
T33	0	4	0	0
T46	0	3	0	1
T48	0	3	0	1
T51	0	3	0	1
T53	0	0	0	1
T54	0	3	0	1
T86	0	19	0	1
T91	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	149212	0	0
T4	1007	313	0	0
T5	16117	0	0	0
T6	798	362	0	0
T8	0	1098	0	0
T15	0	1113	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T39	864	386	0	0
T42	809743	0	0	0
T58	2374	0	0	0
T79	0	1110	0	0
T80	0	1149	0	0
T81	0	1090	0	0
T82	0	1143	0	0
T83	0	281	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	517383	0	292
T1	2911	288	0	0
T2	1241	35	0	0
T3	5722	27	0	0
T4	1007	629	0	0
T5	16117	909	0	0
T7	5330	205	0	0
T10	0	0	0	2
T14	0	0	0	2
T24	1964	19	0	0
T25	2435	14	0	0
T26	1669	1567	0	2
T27	4597	33	0	0
T42	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	2301	0	100
T2	1241	3	0	1
T3	5722	0	0	0
T4	1007	0	0	0
T5	16117	0	0	0
T6	798	0	0	0
T7	5330	0	0	0
T10	0	4	0	0
T24	1964	0	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	3	0	1
T34	0	1	0	0
T46	0	3	0	1
T49	0	4	0	0
T51	0	3	0	1
T52	0	18	0	1
T54	0	18	0	1
T55	0	0	0	1
T88	0	3	0	1
T92	0	0	0	1
T93	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	149212	0	0
T4	1007	313	0	0
T5	16117	0	0	0
T6	798	362	0	0
T8	0	1098	0	0
T15	0	1113	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T39	864	386	0	0
T42	809743	0	0	0
T58	2374	0	0	0
T79	0	1110	0	0
T80	0	1149	0	0
T81	0	1090	0	0
T82	0	1143	0	0
T83	0	281	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	517383	0	292
T1	2911	288	0	0
T2	1241	35	0	0
T3	5722	27	0	0
T4	1007	629	0	0
T5	16117	909	0	0
T7	5330	205	0	0
T10	0	0	0	2
T14	0	0	0	2
T24	1964	19	0	0
T25	2435	14	0	0
T26	1669	1567	0	2
T27	4597	33	0	0
T42	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	4935	0	97
T6	798	0	0	0
T27	4597	3	0	1
T28	1076	0	0	0
T37	0	1	0	0
T39	864	0	0	0
T42	809743	0	0	0
T46	0	59	0	1
T47	4217	67	0	1
T48	1388	0	0	0
T49	1072	0	0	0
T51	0	38	0	1
T58	2374	0	0	0
T59	705	0	0	0
T86	0	61	0	1
T88	0	7	0	1
T93	0	39	0	1
T94	0	1	0	0
T95	0	3	0	1
T96	0	0	0	1
T97	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	149212	0	0
T4	1007	313	0	0
T5	16117	0	0	0
T6	798	362	0	0
T8	0	1098	0	0
T15	0	1113	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T39	864	386	0	0
T42	809743	0	0	0
T58	2374	0	0	0
T79	0	1110	0	0
T80	0	1149	0	0
T81	0	1090	0	0
T82	0	1143	0	0
T83	0	281	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	517383	0	292
T1	2911	288	0	0
T2	1241	35	0	0
T3	5722	27	0	0
T4	1007	629	0	0
T5	16117	909	0	0
T7	5330	205	0	0
T10	0	0	0	2
T14	0	0	0	2
T24	1964	19	0	0
T25	2435	14	0	0
T26	1669	1567	0	2
T27	4597	33	0	0
T42	0	0	0	2
T43	0	0	0	2
T44	0	0	0	2
T58	0	0	0	2
T59	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	5742	0	93
T6	798	0	0	0
T23	0	4	0	0
T27	4597	3	0	1
T28	1076	0	0	0
T36	0	1	0	0
T39	864	1	0	0
T42	809743	0	0	0
T46	0	19	0	1
T47	4217	0	0	0
T48	1388	0	0	0
T49	1072	0	0	0
T51	0	23	0	1
T56	0	8	0	1
T58	2374	0	0	0
T59	705	0	0	0
T88	0	3	0	1
T90	0	0	0	1
T91	0	19	0	1
T92	0	0	0	1
T95	0	0	0	1
T98	0	4	0	0
T99	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	252716756	0	0
T1	2911	2837	0	0
T2	1241	1155	0	0
T3	5722	5664	0	0
T4	1007	883	0	0
T5	16117	15633	0	0
T7	5330	5255	0	0
T24	1964	1897	0	0
T25	2435	2340	0	0
T26	1669	1569	0	0
T27	4597	4513	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	252892838	149212	0	0
T4	1007	313	0	0
T5	16117	0	0	0
T6	798	362	0	0
T8	0	1098	0	0
T15	0	1113	0	0
T25	2435	0	0	0
T26	1669	0	0	0
T27	4597	0	0	0
T28	1076	0	0	0
T39	864	386	0	0
T42	809743	0	0	0
T58	2374	0	0	0
T79	0	1110	0	0
T80	0	1149	0	0
T81	0	1090	0	0
T82	0	1143	0	0
T83	0	281	0	0