Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	253358587	11756640	0	0
boot_gen_cmd_rd_A	253358587	62428	0	0
boot_ins_cmd_rd_A	253358587	70376	0	0
ctrl_rd_A	253358587	63035	0	0
err_code_test_rd_A	253358587	70836	0	0
intr_enable_rd_A	253358587	66930	0	0
max_num_reqs_between_reseeds_rd_A	253358587	62570	0	0
regwen_rd_A	253358587	70376	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253358587	11756640	0	0
T42	809743	284031	0	0
T43	694619	244411	0	0
T44	0	227736	0	0
T45	1268	0	0	0
T46	2738	0	0	0
T47	4217	0	0	0
T48	1388	0	0	0
T49	1072	0	0	0
T58	2374	0	0	0
T59	705	0	0	0
T76	1484	0	0	0
T77	0	186437	0	0
T195	0	403739	0	0
T196	0	11840	0	0
T197	0	299758	0	0
T198	0	61722	0	0
T199	0	349551	0	0
T200	0	261110	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253358587	62428	0	0
T42	809743	7946	0	0
T43	694619	7076	0	0
T45	1268	0	0	0
T46	2738	0	0	0
T47	4217	0	0	0
T48	1388	0	0	0
T49	1072	0	0	0
T58	2374	0	0	0
T59	705	0	0	0
T76	1484	0	0	0
T197	0	8793	0	0
T199	0	9850	0	0
T200	0	4130	0	0
T201	0	2462	0	0
T202	0	4918	0	0
T203	0	1050	0	0
T204	0	1976	0	0
T205	0	3231	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253358587	70376	0	0
T42	809743	9242	0	0
T43	694619	8249	0	0
T45	1268	0	0	0
T46	2738	0	0	0
T47	4217	0	0	0
T48	1388	0	0	0
T49	1072	0	0	0
T58	2374	0	0	0
T59	705	0	0	0
T76	1484	0	0	0
T197	0	9903	0	0
T199	0	11197	0	0
T200	0	4689	0	0
T201	0	3014	0	0
T202	0	5254	0	0
T203	0	1096	0	0
T204	0	2365	0	0
T205	0	3319	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253358587	63035	0	0
T9	0	7	0	0
T29	0	4	0	0
T42	809743	7954	0	0
T43	694619	7031	0	0
T45	1268	0	0	0
T46	2738	0	0	0
T47	4217	0	0	0
T48	1388	0	0	0
T49	1072	0	0	0
T58	2374	0	0	0
T59	705	0	0	0
T60	0	4	0	0
T76	1484	0	0	0
T197	0	9031	0	0
T199	0	10001	0	0
T200	0	4093	0	0
T201	0	2620	0	0
T202	0	4790	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253358587	70836	0	0
T42	809743	9148	0	0
T43	694619	7751	0	0
T45	1268	0	0	0
T46	2738	0	0	0
T47	4217	0	0	0
T48	1388	0	0	0
T49	1072	0	0	0
T58	2374	0	0	0
T59	705	0	0	0
T76	1484	0	0	0
T197	0	10132	0	0
T199	0	11809	0	0
T200	0	4559	0	0
T201	0	3006	0	0
T202	0	5334	0	0
T203	0	1129	0	0
T204	0	2484	0	0
T205	0	3324	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253358587	66930	0	0
T42	809743	8460	0	0
T43	694619	7429	0	0
T45	1268	0	0	0
T46	2738	0	0	0
T47	4217	0	0	0
T48	1388	0	0	0
T49	1072	0	0	0
T58	2374	0	0	0
T59	705	0	0	0
T76	1484	0	0	0
T197	0	9064	0	0
T199	0	10384	0	0
T200	0	3923	0	0
T201	0	2587	0	0
T202	0	5504	0	0
T203	0	1106	0	0
T204	0	2263	0	0
T206	0	76	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253358587	62570	0	0
T42	809743	7930	0	0
T43	694619	7141	0	0
T45	1268	0	0	0
T46	2738	0	0	0
T47	4217	0	0	0
T48	1388	0	0	0
T49	1072	0	0	0
T58	2374	0	0	0
T59	705	0	0	0
T76	1484	0	0	0
T197	0	8702	0	0
T199	0	10218	0	0
T200	0	4183	0	0
T201	0	2785	0	0
T202	0	4740	0	0
T203	0	996	0	0
T204	0	2058	0	0
T205	0	2965	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	253358587	70376	0	0
T42	809743	9012	0	0
T43	694619	7714	0	0
T45	1268	0	0	0
T46	2738	0	0	0
T47	4217	0	0	0
T48	1388	0	0	0
T49	1072	0	0	0
T58	2374	0	0	0
T59	705	0	0	0
T76	1484	0	0	0
T197	0	9688	0	0
T199	0	10876	0	0
T200	0	4425	0	0
T201	0	3006	0	0
T202	0	5932	0	0
T203	0	1125	0	0
T204	0	2414	0	0
T205	0	3265	0	0