Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.44 83.33 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.71 98.24 93.82 97.01 82.66 96.76 99.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 92.67 99.92 92.48 82.54 82.66 99.52 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.95 95.02 97.57 100.00 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT9,T28,T29

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T16,T17
10CoveredT5,T6,T7

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1170 1170 100.00
Total Bits 0->1 585 585 100.00
Total Bits 1->0 585 585 100.00

Ports 69 69 100.00
Port Bits 1170 1170 100.00
Port Bits 0->1 585 585 100.00
Port Bits 1->0 585 585 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T22 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T2,T4,T37 Yes T2,T4,T37 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_source[7:0] Yes Yes T1,T2,T9 Yes T1,T2,T9 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T4,T38,T39 Yes T4,T38,T39 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T1,T2,T9 Yes T1,T2,T9 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
edn_i[1].edn_req Yes Yes T1,T40,T19 Yes T1,T40,T19 INPUT
edn_i[2].edn_req Yes Yes T1,T41,T19 Yes T1,T41,T19 INPUT
edn_i[3].edn_req Yes Yes T1,T41,T28 Yes T1,T41,T28 INPUT
edn_i[4].edn_req Yes Yes T1,T41,T42 Yes T1,T41,T42 INPUT
edn_i[5].edn_req Yes Yes T5,T40,T41 Yes T5,T40,T41 INPUT
edn_i[6].edn_req Yes Yes T1,T40,T41 Yes T1,T40,T41 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[0].edn_fips Yes Yes T2,T3,T22 Yes T1,T2,T3 OUTPUT
edn_o[0].edn_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T1,T19,T10 Yes T1,T40,T19 OUTPUT
edn_o[1].edn_fips Yes Yes T1,T19,T43 Yes T1,T40,T19 OUTPUT
edn_o[1].edn_ack Yes Yes T1,T40,T19 Yes T1,T40,T19 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T1,T41,T19 Yes T1,T41,T19 OUTPUT
edn_o[2].edn_fips Yes Yes T41,T44,T45 Yes T41,T10,T44 OUTPUT
edn_o[2].edn_ack Yes Yes T1,T41,T19 Yes T1,T41,T19 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T1,T41,T28 Yes T1,T41,T28 OUTPUT
edn_o[3].edn_fips Yes Yes T43,T46,T47 Yes T1,T41,T28 OUTPUT
edn_o[3].edn_ack Yes Yes T1,T41,T28 Yes T1,T41,T28 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T41,T42,T27 Yes T1,T41,T42 OUTPUT
edn_o[4].edn_fips Yes Yes T41,T42,T10 Yes T41,T42,T27 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T41,T42 Yes T1,T41,T42 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T40,T42,T10 Yes T40,T41,T42 OUTPUT
edn_o[5].edn_fips Yes Yes T40,T44,T46 Yes T40,T44,T48 OUTPUT
edn_o[5].edn_ack Yes Yes T40,T41,T42 Yes T40,T41,T42 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T1,T40,T41 Yes T1,T40,T41 OUTPUT
edn_o[6].edn_fips Yes Yes T1,T40,T41 Yes T1,T40,T41 OUTPUT
edn_o[6].edn_ack Yes Yes T1,T40,T41 Yes T1,T40,T41 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_fips Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[1:0] Yes Yes T28,T29,T49 Yes T28,T29,T49 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T9,T21,T50 Yes T9,T21,T50 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T21,T5,T6 Yes T21,T5,T6 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T9,T21,T50 Yes T9,T21,T50 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T21,T5,T6 Yes T21,T5,T6 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T4,T51,T38 Yes T4,T51,T38 OUTPUT
intr_edn_fatal_err_o Yes Yes T4,T51,T30 Yes T4,T51,T30 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 47 47 100.00 47 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 47 47 100.00 47 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 195727166 195538573 0 0
CsrngAppIfOut_A 195727166 195538573 0 0
FpvSecCmCntAlertCheck_A 195727166 140 0 0
FpvSecCmGenCmdFifoRptrCheck_A 195727166 90 0 0
FpvSecCmGenCmdFifoWptrCheck_A 195727166 90 0 0
FpvSecCmMainFsmCheck_A 195727166 90 0 0
FpvSecCmRegWeOnehotCheck_A 195727166 90 0 0
FpvSecCmResCmdFifoRptrCheck_A 195727166 90 0 0
FpvSecCmResCmdFifoWptrCheck_A 195727166 90 0 0
IntrEdnCmdReqDoneKnownO_A 195727166 195538573 0 0
TlAReadyKnownO_A 195727166 195538573 0 0
TlDValidKnownO_A 195727166 195538573 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 195727166 90 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 195727166 90 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 195727166 90 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 195727166 90 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 195727166 90 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 195727166 90 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 195727166 90 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 195727166 550619 0 312
gen_edn_if_asserts[0].EdnDataStable_A 195727166 29472 0 371
gen_edn_if_asserts[0].EdnEndPointOut_A 195727166 195538573 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 195727166 160426 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 195727166 550619 0 312
gen_edn_if_asserts[1].EdnDataStable_A 195727166 4331 0 107
gen_edn_if_asserts[1].EdnEndPointOut_A 195727166 195538573 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 195727166 160426 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 195727166 550619 0 312
gen_edn_if_asserts[2].EdnDataStable_A 195727166 4515 0 115
gen_edn_if_asserts[2].EdnEndPointOut_A 195727166 195538573 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 195727166 160426 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 195727166 550619 0 312
gen_edn_if_asserts[3].EdnDataStable_A 195727166 5899 0 98
gen_edn_if_asserts[3].EdnEndPointOut_A 195727166 195538573 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 195727166 160426 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 195727166 550619 0 312
gen_edn_if_asserts[4].EdnDataStable_A 195727166 1792 0 97
gen_edn_if_asserts[4].EdnEndPointOut_A 195727166 195538573 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 195727166 160426 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 195727166 550619 0 312
gen_edn_if_asserts[5].EdnDataStable_A 195727166 1778 0 85
gen_edn_if_asserts[5].EdnEndPointOut_A 195727166 195538573 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 195727166 160426 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 195727166 550619 0 312
gen_edn_if_asserts[6].EdnDataStable_A 195727166 3865 0 85
gen_edn_if_asserts[6].EdnEndPointOut_A 195727166 195538573 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 195727166 160426 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 140 0 0
T8 763 1 0 0
T11 1949 0 0 0
T13 2479 1 0 0
T14 2392 1 0 0
T15 0 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T39 259480 0 0 0
T52 0 1 0 0
T53 0 1 0 0
T54 0 20 0 0
T55 0 1 0 0
T56 1107 0 0 0
T57 2180 0 0 0
T58 1965 0 0 0
T59 2984 0 0 0
T60 3541 0 0 0

FpvSecCmGenCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

FpvSecCmGenCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

FpvSecCmResCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

FpvSecCmResCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 90 0 0
T15 60667 20 0 0
T16 0 20 0 0
T17 0 10 0 0
T52 1654 0 0 0
T54 0 20 0 0
T61 0 20 0 0
T62 1928 0 0 0
T63 941 0 0 0
T64 2918 0 0 0
T65 1626 0 0 0
T66 1448 0 0 0
T67 1426 0 0 0
T68 8313 0 0 0
T69 1160 0 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 550619 0 312
T1 2438 95 0 0
T2 4698 212 0 0
T3 1257 79 0 0
T4 355408 1057 0 2
T5 1535 910 0 0
T9 2412 133 0 0
T15 0 0 0 2
T18 3661 242 0 0
T20 1515 21 0 0
T21 1108 1024 0 2
T22 1461 18 0 0
T38 0 0 0 2
T48 0 0 0 2
T50 0 0 0 2
T65 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 29472 0 371
T1 2438 3 0 1
T2 4698 579 0 1
T3 1257 37 0 1
T4 355408 92 0 0
T5 1535 0 0 0
T9 2412 4 0 1
T18 3661 15 0 1
T20 1515 3 0 1
T21 1108 0 0 0
T22 1461 42 0 1
T40 0 22 0 1
T41 0 3 0 1
T51 0 0 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 160426 0 0
T5 1535 634 0 0
T6 1821 1106 0 0
T7 2260 726 0 0
T8 0 364 0 0
T13 0 1140 0 0
T14 0 734 0 0
T15 0 19294 0 0
T18 3661 0 0 0
T19 3561 0 0 0
T30 0 7 0 0
T40 1694 0 0 0
T41 2961 0 0 0
T51 10140 0 0 0
T52 0 1014 0 0
T73 0 332 0 0
T74 1943 0 0 0
T75 1921 0 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 550619 0 312
T1 2438 95 0 0
T2 4698 212 0 0
T3 1257 79 0 0
T4 355408 1057 0 2
T5 1535 910 0 0
T9 2412 133 0 0
T15 0 0 0 2
T18 3661 242 0 0
T20 1515 21 0 0
T21 1108 1024 0 2
T22 1461 18 0 0
T38 0 0 0 2
T48 0 0 0 2
T50 0 0 0 2
T65 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 4331 0 107
T1 2438 19 0 1
T2 4698 0 0 0
T3 1257 0 0 0
T4 355408 0 0 0
T5 1535 0 0 0
T9 2412 0 0 0
T10 0 3 0 1
T18 3661 0 0 0
T19 0 15 0 1
T20 1515 0 0 0
T21 1108 0 0 0
T22 1461 0 0 0
T40 0 3 0 1
T43 0 13 0 1
T44 0 21 0 1
T46 0 3 0 1
T49 0 4 0 1
T57 0 45 0 1
T64 0 46 0 1

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 160426 0 0
T5 1535 634 0 0
T6 1821 1106 0 0
T7 2260 726 0 0
T8 0 364 0 0
T13 0 1140 0 0
T14 0 734 0 0
T15 0 19294 0 0
T18 3661 0 0 0
T19 3561 0 0 0
T30 0 7 0 0
T40 1694 0 0 0
T41 2961 0 0 0
T51 10140 0 0 0
T52 0 1014 0 0
T73 0 332 0 0
T74 1943 0 0 0
T75 1921 0 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 550619 0 312
T1 2438 95 0 0
T2 4698 212 0 0
T3 1257 79 0 0
T4 355408 1057 0 2
T5 1535 910 0 0
T9 2412 133 0 0
T15 0 0 0 2
T18 3661 242 0 0
T20 1515 21 0 0
T21 1108 1024 0 2
T22 1461 18 0 0
T38 0 0 0 2
T48 0 0 0 2
T50 0 0 0 2
T65 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 4515 0 115
T1 2438 3 0 1
T2 4698 0 0 0
T3 1257 0 0 0
T4 355408 0 0 0
T5 1535 0 0 0
T9 2412 0 0 0
T10 0 3 0 1
T18 3661 0 0 0
T19 0 3 0 1
T20 1515 0 0 0
T21 1108 0 0 0
T22 1461 0 0 0
T41 0 19 0 1
T43 0 3 0 1
T44 0 42 0 1
T47 0 3 0 1
T64 0 0 0 1
T72 0 1 0 0
T76 0 3 0 1
T77 0 4 0 1

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 160426 0 0
T5 1535 634 0 0
T6 1821 1106 0 0
T7 2260 726 0 0
T8 0 364 0 0
T13 0 1140 0 0
T14 0 734 0 0
T15 0 19294 0 0
T18 3661 0 0 0
T19 3561 0 0 0
T30 0 7 0 0
T40 1694 0 0 0
T41 2961 0 0 0
T51 10140 0 0 0
T52 0 1014 0 0
T73 0 332 0 0
T74 1943 0 0 0
T75 1921 0 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 550619 0 312
T1 2438 95 0 0
T2 4698 212 0 0
T3 1257 79 0 0
T4 355408 1057 0 2
T5 1535 910 0 0
T9 2412 133 0 0
T15 0 0 0 2
T18 3661 242 0 0
T20 1515 21 0 0
T21 1108 1024 0 2
T22 1461 18 0 0
T38 0 0 0 2
T48 0 0 0 2
T50 0 0 0 2
T65 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 5899 0 98
T1 2438 3 0 1
T2 4698 0 0 0
T3 1257 0 0 0
T4 355408 0 0 0
T5 1535 0 0 0
T9 2412 0 0 0
T18 3661 0 0 0
T20 1515 0 0 0
T21 1108 0 0 0
T22 1461 0 0 0
T28 0 4 0 1
T41 0 3 0 1
T43 0 10 0 1
T44 0 3 0 1
T46 0 9 0 1
T47 0 42 0 1
T64 0 3 0 1
T76 0 3 0 1
T78 0 3 0 1

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 160426 0 0
T5 1535 634 0 0
T6 1821 1106 0 0
T7 2260 726 0 0
T8 0 364 0 0
T13 0 1140 0 0
T14 0 734 0 0
T15 0 19294 0 0
T18 3661 0 0 0
T19 3561 0 0 0
T30 0 7 0 0
T40 1694 0 0 0
T41 2961 0 0 0
T51 10140 0 0 0
T52 0 1014 0 0
T73 0 332 0 0
T74 1943 0 0 0
T75 1921 0 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 550619 0 312
T1 2438 95 0 0
T2 4698 212 0 0
T3 1257 79 0 0
T4 355408 1057 0 2
T5 1535 910 0 0
T9 2412 133 0 0
T15 0 0 0 2
T18 3661 242 0 0
T20 1515 21 0 0
T21 1108 1024 0 2
T22 1461 18 0 0
T38 0 0 0 2
T48 0 0 0 2
T50 0 0 0 2
T65 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 1792 0 97
T1 2438 3 0 1
T2 4698 0 0 0
T3 1257 0 0 0
T4 355408 0 0 0
T5 1535 0 0 0
T9 2412 0 0 0
T10 0 40 0 1
T18 3661 0 0 0
T20 1515 0 0 0
T21 1108 0 0 0
T22 1461 0 0 0
T27 0 3 0 1
T41 0 46 0 1
T42 0 15 0 1
T43 0 54 0 1
T44 0 62 0 1
T56 0 3 0 1
T76 0 23 0 1
T79 0 50 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 160426 0 0
T5 1535 634 0 0
T6 1821 1106 0 0
T7 2260 726 0 0
T8 0 364 0 0
T13 0 1140 0 0
T14 0 734 0 0
T15 0 19294 0 0
T18 3661 0 0 0
T19 3561 0 0 0
T30 0 7 0 0
T40 1694 0 0 0
T41 2961 0 0 0
T51 10140 0 0 0
T52 0 1014 0 0
T73 0 332 0 0
T74 1943 0 0 0
T75 1921 0 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 550619 0 312
T1 2438 95 0 0
T2 4698 212 0 0
T3 1257 79 0 0
T4 355408 1057 0 2
T5 1535 910 0 0
T9 2412 133 0 0
T15 0 0 0 2
T18 3661 242 0 0
T20 1515 21 0 0
T21 1108 1024 0 2
T22 1461 18 0 0
T38 0 0 0 2
T48 0 0 0 2
T50 0 0 0 2
T65 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 1778 0 85
T6 1821 0 0 0
T7 2260 0 0 0
T10 0 3 0 1
T19 3561 0 0 0
T30 1512 0 0 0
T37 1643 0 0 0
T40 1694 63 0 1
T41 2961 3 0 1
T42 0 3 0 1
T44 0 27 0 1
T46 0 19 0 1
T47 0 3 0 1
T48 0 4 0 0
T51 10140 0 0 0
T64 0 0 0 1
T74 1943 0 0 0
T75 1921 0 0 0
T79 0 3 0 1
T80 0 3 0 1

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 160426 0 0
T5 1535 634 0 0
T6 1821 1106 0 0
T7 2260 726 0 0
T8 0 364 0 0
T13 0 1140 0 0
T14 0 734 0 0
T15 0 19294 0 0
T18 3661 0 0 0
T19 3561 0 0 0
T30 0 7 0 0
T40 1694 0 0 0
T41 2961 0 0 0
T51 10140 0 0 0
T52 0 1014 0 0
T73 0 332 0 0
T74 1943 0 0 0
T75 1921 0 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 550619 0 312
T1 2438 95 0 0
T2 4698 212 0 0
T3 1257 79 0 0
T4 355408 1057 0 2
T5 1535 910 0 0
T9 2412 133 0 0
T15 0 0 0 2
T18 3661 242 0 0
T20 1515 21 0 0
T21 1108 1024 0 2
T22 1461 18 0 0
T38 0 0 0 2
T48 0 0 0 2
T50 0 0 0 2
T65 0 0 0 2
T70 0 0 0 2
T71 0 0 0 2
T72 0 0 0 2

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 3865 0 85
T1 2438 22 0 1
T2 4698 0 0 0
T3 1257 0 0 0
T4 355408 0 0 0
T5 1535 0 0 0
T9 2412 0 0 0
T10 0 61 0 1
T18 3661 0 0 0
T20 1515 0 0 0
T21 1108 0 0 0
T22 1461 0 0 0
T40 0 42 0 1
T41 0 14 0 1
T46 0 3 0 1
T63 0 3 0 1
T64 0 30 0 1
T72 0 4 0 0
T81 0 3 0 1
T82 0 35 0 1
T83 0 0 0 1

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 195538573 0 0
T1 2438 2379 0 0
T2 4698 4626 0 0
T3 1257 1166 0 0
T4 355408 355395 0 0
T5 1535 1391 0 0
T9 2412 2354 0 0
T18 3661 3567 0 0
T20 1515 1426 0 0
T21 1108 1026 0 0
T22 1461 1362 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 195727166 160426 0 0
T5 1535 634 0 0
T6 1821 1106 0 0
T7 2260 726 0 0
T8 0 364 0 0
T13 0 1140 0 0
T14 0 734 0 0
T15 0 19294 0 0
T18 3661 0 0 0
T19 3561 0 0 0
T30 0 7 0 0
T40 1694 0 0 0
T41 2961 0 0 0
T51 10140 0 0 0
T52 0 1014 0 0
T73 0 332 0 0
T74 1943 0 0 0
T75 1921 0 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%