Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	196212089	8711328	0	0
boot_gen_cmd_rd_A	196212089	53246	0	0
boot_ins_cmd_rd_A	196212089	61916	0	0
ctrl_rd_A	196212089	54129	0	0
err_code_test_rd_A	196212089	61740	0	0
intr_enable_rd_A	196212089	59347	0	0
max_num_reqs_between_reseeds_rd_A	196212089	53939	0	0
regwen_rd_A	196212089	61387	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196212089	8711328	0	0
T4	355408	200619	0	0
T5	1535	0	0	0
T6	1821	0	0	0
T18	3661	0	0	0
T19	3561	0	0	0
T38	0	235083	0	0
T39	0	146561	0	0
T40	1694	0	0	0
T41	2961	0	0	0
T51	10140	0	0	0
T74	1943	0	0	0
T75	1921	0	0	0
T153	0	201535	0	0
T193	0	126038	0	0
T194	0	70574	0	0
T195	0	202112	0	0
T196	0	247173	0	0
T197	0	157642	0	0
T198	0	50809	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196212089	53246	0	0
T130	1907	0	0	0
T194	189630	1011	0	0
T195	0	2999	0	0
T199	0	5698	0	0
T200	0	5240	0	0
T201	0	6152	0	0
T202	0	953	0	0
T203	0	1888	0	0
T204	0	7982	0	0
T205	0	2060	0	0
T206	0	3370	0	0
T207	932	0	0	0
T208	1183	0	0	0
T209	3937	0	0	0
T210	2678	0	0	0
T211	1298	0	0	0
T212	2505	0	0	0
T213	1710	0	0	0
T214	4256	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196212089	61916	0	0
T130	1907	0	0	0
T194	189630	1379	0	0
T195	0	3643	0	0
T199	0	6602	0	0
T200	0	6233	0	0
T201	0	7516	0	0
T202	0	1006	0	0
T203	0	2344	0	0
T204	0	8764	0	0
T205	0	2339	0	0
T206	0	3752	0	0
T207	932	0	0	0
T208	1183	0	0	0
T209	3937	0	0	0
T210	2678	0	0	0
T211	1298	0	0	0
T212	2505	0	0	0
T213	1710	0	0	0
T214	4256	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196212089	54129	0	0
T23	1676	7	0	0
T24	0	5	0	0
T26	1132	0	0	0
T27	1290	0	0	0
T28	2214	7	0	0
T29	1819	0	0	0
T38	588507	0	0	0
T42	4072	0	0	0
T50	1746	0	0	0
T85	0	1	0	0
T115	0	1	0	0
T118	0	5	0	0
T194	0	1088	0	0
T209	0	6	0	0
T215	0	6	0	0
T216	0	4	0	0
T217	4712	0	0	0
T218	5749	0	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196212089	61740	0	0
T130	1907	0	0	0
T194	189630	1209	0	0
T195	0	3434	0	0
T199	0	6695	0	0
T200	0	6333	0	0
T201	0	7049	0	0
T202	0	1221	0	0
T203	0	2439	0	0
T204	0	8601	0	0
T205	0	2499	0	0
T206	0	3681	0	0
T207	932	0	0	0
T208	1183	0	0	0
T209	3937	0	0	0
T210	2678	0	0	0
T211	1298	0	0	0
T212	2505	0	0	0
T213	1710	0	0	0
T214	4256	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196212089	59347	0	0
T8	763	0	0	0
T13	2479	0	0	0
T43	4519	0	0	0
T44	2222	0	0	0
T49	2552	0	0	0
T56	1107	0	0	0
T76	1745	0	0	0
T152	13723	0	0	0
T154	26806	87	0	0
T159	0	37	0	0
T192	2187	0	0	0
T194	0	1245	0	0
T195	0	3349	0	0
T199	0	6080	0	0
T200	0	5597	0	0
T219	0	10	0	0
T220	0	107	0	0
T221	0	73	0	0
T222	0	48	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196212089	53939	0	0
T130	1907	0	0	0
T194	189630	1125	0	0
T195	0	3075	0	0
T199	0	5818	0	0
T200	0	5445	0	0
T201	0	5934	0	0
T202	0	997	0	0
T203	0	1928	0	0
T204	0	7562	0	0
T205	0	2148	0	0
T206	0	3357	0	0
T207	932	0	0	0
T208	1183	0	0	0
T209	3937	0	0	0
T210	2678	0	0	0
T211	1298	0	0	0
T212	2505	0	0	0
T213	1710	0	0	0
T214	4256	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	196212089	61387	0	0
T130	1907	0	0	0
T194	189630	1260	0	0
T195	0	3571	0	0
T199	0	6484	0	0
T200	0	6134	0	0
T201	0	7010	0	0
T202	0	981	0	0
T203	0	2466	0	0
T204	0	8200	0	0
T205	0	2402	0	0
T206	0	4063	0	0
T207	932	0	0	0
T208	1183	0	0	0
T209	3937	0	0	0
T210	2678	0	0	0
T211	1298	0	0	0
T212	2505	0	0	0
T213	1710	0	0	0
T214	4256	0	0	0