Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : edn
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut 94.44 83.33 100.00 100.00



Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.44 83.33 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.64 98.24 93.64 91.35 82.08 96.76 99.77


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
edn_csr_assert 100.00 100.00
gen_alert_tx[0].u_prim_alert_sender 100.00 100.00
gen_alert_tx[1].u_prim_alert_sender 100.00 100.00
tlul_assert_device 100.00 100.00 100.00 100.00
u_edn_core 87.00 99.92 92.21 49.41 82.08 99.52 98.88
u_edn_cov_if 25.00 50.00 0.00
u_reg 96.95 95.02 97.57 100.00 92.16 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Cond Coverage for Module : edn
TotalCoveredPercent
Conditions6583.33
Logical6583.33
Non-Logical00
Event00

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT28,T29,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT12,T15,T16
10CoveredT2,T5,T34

Toggle Coverage for Module : edn
TotalCoveredPercent
Totals 69 69 100.00
Total Bits 1170 1170 100.00
Total Bits 0->1 585 585 100.00
Total Bits 1->0 585 585 100.00

Ports 69 69 100.00
Port Bits 1170 1170 100.00
Port Bits 0->1 585 585 100.00
Port Bits 1->0 585 585 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T2,T4,T5 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T4,T19,T8 Yes T4,T19,T8 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T2,T3,T4 INPUT
tl_i.a_address[31:0] Yes Yes T2,T4,T19 Yes T2,T4,T19 INPUT
tl_i.a_source[7:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 INPUT
tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_error Yes Yes T39,T40,T41 Yes T39,T40,T41 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T2,T3,T4 Yes T2,T3,T4 OUTPUT
tl_o.d_user.rsp_intg[5:0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
tl_o.d_source[7:0] Yes Yes T2,T3,T4 Yes T1,T2,T3 OUTPUT
tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T2,*T3,*T4 Yes T1,T2,T3 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
edn_i[0].edn_req Yes Yes T4,T19,T20 Yes T4,T19,T20 INPUT
edn_i[1].edn_req Yes Yes T20,T11,T17 Yes T20,T11,T17 INPUT
edn_i[2].edn_req Yes Yes T2,T3,T20 Yes T2,T3,T20 INPUT
edn_i[3].edn_req Yes Yes T20,T11,T17 Yes T20,T11,T17 INPUT
edn_i[4].edn_req Yes Yes T1,T20,T11 Yes T1,T20,T11 INPUT
edn_i[5].edn_req Yes Yes T20,T22,T11 Yes T20,T22,T11 INPUT
edn_i[6].edn_req Yes Yes T20,T11,T5 Yes T20,T11,T5 INPUT
edn_o[0].edn_bus[31:0] Yes Yes T4,T19,T20 Yes T4,T19,T20 OUTPUT
edn_o[0].edn_fips Yes Yes T19,T20,T8 Yes T4,T19,T20 OUTPUT
edn_o[0].edn_ack Yes Yes T4,T19,T20 Yes T4,T19,T20 OUTPUT
edn_o[1].edn_bus[31:0] Yes Yes T20,T11,T17 Yes T20,T11,T17 OUTPUT
edn_o[1].edn_fips Yes Yes T11,T17,T27 Yes T20,T11,T17 OUTPUT
edn_o[1].edn_ack Yes Yes T20,T11,T17 Yes T20,T11,T17 OUTPUT
edn_o[2].edn_bus[31:0] Yes Yes T3,T20,T17 Yes T3,T20,T17 OUTPUT
edn_o[2].edn_fips Yes Yes T2,T20,T42 Yes T2,T3,T20 OUTPUT
edn_o[2].edn_ack Yes Yes T2,T3,T20 Yes T2,T3,T20 OUTPUT
edn_o[3].edn_bus[31:0] Yes Yes T20,T11,T17 Yes T20,T11,T17 OUTPUT
edn_o[3].edn_fips Yes Yes T20,T11,T17 Yes T20,T11,T17 OUTPUT
edn_o[3].edn_ack Yes Yes T20,T11,T17 Yes T20,T11,T17 OUTPUT
edn_o[4].edn_bus[31:0] Yes Yes T1,T20,T17 Yes T1,T20,T17 OUTPUT
edn_o[4].edn_fips Yes Yes T17,T27,T43 Yes T1,T11,T17 OUTPUT
edn_o[4].edn_ack Yes Yes T1,T20,T11 Yes T1,T20,T11 OUTPUT
edn_o[5].edn_bus[31:0] Yes Yes T20,T22,T11 Yes T20,T22,T11 OUTPUT
edn_o[5].edn_fips Yes Yes T20,T11,T42 Yes T20,T11,T44 OUTPUT
edn_o[5].edn_ack Yes Yes T20,T22,T11 Yes T20,T22,T11 OUTPUT
edn_o[6].edn_bus[31:0] Yes Yes T20,T11,T45 Yes T20,T11,T42 OUTPUT
edn_o[6].edn_fips Yes Yes T20,T11,T45 Yes T20,T11,T45 OUTPUT
edn_o[6].edn_ack Yes Yes T20,T11,T17 Yes T20,T11,T17 OUTPUT
csrng_cmd_o.genbits_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_bus[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_o.csrng_req_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
csrng_cmd_i.genbits_bus[127:0] Yes Yes T19,T20,T8 Yes T19,T20,T8 INPUT
csrng_cmd_i.genbits_fips Yes Yes T3,T19,T20 Yes T19,T20,T8 INPUT
csrng_cmd_i.genbits_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_rsp_sts[1:0] Yes Yes T28,T29,T46 Yes T28,T29,T46 INPUT
csrng_cmd_i.csrng_rsp_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
csrng_cmd_i.csrng_req_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T21,T28,T29 Yes T21,T28,T29 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T2,T21,T5 Yes T2,T21,T5 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T21,T28,T29 Yes T21,T28,T29 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T2,T21,T5 Yes T2,T21,T5 OUTPUT
intr_edn_cmd_req_done_o Yes Yes T4,T47,T48 Yes T4,T47,T48 OUTPUT
intr_edn_fatal_err_o Yes Yes T2,T4,T47 Yes T2,T4,T47 OUTPUT

*Tests covering at least one bit in the range

Assert Coverage for Module : edn
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 47 47 100.00 47 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 47 47 100.00 47 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
AlertTxKnownO_A 185001714 184847208 0 0
CsrngAppIfOut_A 185001714 184847208 0 0
FpvSecCmCntAlertCheck_A 185001714 96 0 0
FpvSecCmGenCmdFifoRptrCheck_A 185001714 60 0 0
FpvSecCmGenCmdFifoWptrCheck_A 185001714 60 0 0
FpvSecCmMainFsmCheck_A 185001714 60 0 0
FpvSecCmRegWeOnehotCheck_A 185001714 60 0 0
FpvSecCmResCmdFifoRptrCheck_A 185001714 60 0 0
FpvSecCmResCmdFifoWptrCheck_A 185001714 60 0 0
IntrEdnCmdReqDoneKnownO_A 185001714 184847208 0 0
TlAReadyKnownO_A 185001714 184847208 0 0
TlDValidKnownO_A 185001714 184847208 0 0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A 185001714 60 0 0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A 185001714 60 0 0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A 185001714 60 0 0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A 185001714 60 0 0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A 185001714 60 0 0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A 185001714 60 0 0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A 185001714 60 0 0
gen_edn_if_asserts[0].EdnDataStableDisable_A 185001714 477225 0 300
gen_edn_if_asserts[0].EdnDataStable_A 185001714 21933 0 360
gen_edn_if_asserts[0].EdnEndPointOut_A 185001714 184847208 0 0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A 185001714 143886 0 0
gen_edn_if_asserts[1].EdnDataStableDisable_A 185001714 477225 0 300
gen_edn_if_asserts[1].EdnDataStable_A 185001714 5345 0 115
gen_edn_if_asserts[1].EdnEndPointOut_A 185001714 184847208 0 0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A 185001714 143886 0 0
gen_edn_if_asserts[2].EdnDataStableDisable_A 185001714 477225 0 300
gen_edn_if_asserts[2].EdnDataStable_A 185001714 4631 0 104
gen_edn_if_asserts[2].EdnEndPointOut_A 185001714 184847208 0 0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A 185001714 143886 0 0
gen_edn_if_asserts[3].EdnDataStableDisable_A 185001714 477225 0 300
gen_edn_if_asserts[3].EdnDataStable_A 185001714 5352 0 93
gen_edn_if_asserts[3].EdnEndPointOut_A 185001714 184847208 0 0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A 185001714 143886 0 0
gen_edn_if_asserts[4].EdnDataStableDisable_A 185001714 477225 0 300
gen_edn_if_asserts[4].EdnDataStable_A 185001714 4614 0 101
gen_edn_if_asserts[4].EdnEndPointOut_A 185001714 184847208 0 0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A 185001714 143886 0 0
gen_edn_if_asserts[5].EdnDataStableDisable_A 185001714 477225 0 300
gen_edn_if_asserts[5].EdnDataStable_A 185001714 2494 0 78
gen_edn_if_asserts[5].EdnEndPointOut_A 185001714 184847208 0 0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A 185001714 143886 0 0
gen_edn_if_asserts[6].EdnDataStableDisable_A 185001714 477225 0 300
gen_edn_if_asserts[6].EdnDataStable_A 185001714 2977 0 76
gen_edn_if_asserts[6].EdnEndPointOut_A 185001714 184847208 0 0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A 185001714 143886 0 0


AlertTxKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

CsrngAppIfOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

FpvSecCmCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 96 0 0
T12 24991 10 0 0
T13 580 1 0 0
T14 0 1 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T49 0 1 0 0
T50 0 1 0 0
T51 0 1 0 0
T52 0 1 0 0
T53 0 1 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0

FpvSecCmGenCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

FpvSecCmGenCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

FpvSecCmMainFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

FpvSecCmResCmdFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

FpvSecCmResCmdFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

IntrEdnCmdReqDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 60 0 0
T12 24991 10 0 0
T13 580 0 0 0
T15 0 10 0 0
T16 0 20 0 0
T29 1909 0 0 0
T31 2200 0 0 0
T33 603 0 0 0
T42 3295 0 0 0
T54 1329 0 0 0
T55 1259 0 0 0
T56 1064 0 0 0
T57 2610 0 0 0
T58 0 10 0 0
T59 0 10 0 0

gen_edn_if_asserts[0].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 477225 0 300
T1 1057 40 0 0
T2 2200 1019 0 0
T3 3250 1721 0 2
T4 7434 865 0 0
T8 3371 90 0 0
T12 0 0 0 2
T18 0 0 0 2
T19 2526 26 0 0
T20 5691 27 0 0
T21 1333 1236 0 2
T22 1860 12 0 0
T23 1578 18 0 0
T40 0 0 0 2
T55 0 0 0 2
T60 0 0 0 2
T61 0 0 0 2
T62 0 0 0 2
T63 0 0 0 2

gen_edn_if_asserts[0].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 21933 0 360
T4 7434 3 0 1
T5 1202 0 0 0
T8 3371 35 0 1
T11 3497 0 0 0
T17 0 3 0 1
T19 2526 68 0 1
T20 5691 58 0 1
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 3 0 1
T28 0 4 0 1
T44 0 25 0 1
T47 0 21 0 1
T64 1023 3 0 1

gen_edn_if_asserts[0].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 143886 0 0
T2 2200 1117 0 0
T3 3250 0 0 0
T4 7434 0 0 0
T5 0 632 0 0
T6 0 600 0 0
T8 3371 0 0 0
T11 3497 0 0 0
T12 0 7463 0 0
T13 0 230 0 0
T19 2526 0 0 0
T20 5691 0 0 0
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T31 0 31 0 0
T33 0 17 0 0
T34 0 592 0 0
T65 0 248 0 0
T66 0 380 0 0

gen_edn_if_asserts[1].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 477225 0 300
T1 1057 40 0 0
T2 2200 1019 0 0
T3 3250 1721 0 2
T4 7434 865 0 0
T8 3371 90 0 0
T12 0 0 0 2
T18 0 0 0 2
T19 2526 26 0 0
T20 5691 27 0 0
T21 1333 1236 0 2
T22 1860 12 0 0
T23 1578 18 0 0
T40 0 0 0 2
T55 0 0 0 2
T60 0 0 0 2
T61 0 0 0 2
T62 0 0 0 2
T63 0 0 0 2

gen_edn_if_asserts[1].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 5345 0 115
T5 1202 0 0 0
T8 3371 0 0 0
T9 0 37 0 1
T11 3497 32 0 1
T17 8524 57 0 1
T20 5691 3 0 1
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T27 0 78 0 1
T28 2423 0 0 0
T42 0 7 0 1
T43 0 0 0 1
T44 0 26 0 1
T57 0 16 0 1
T64 1023 0 0 0
T67 0 3 0 1
T68 0 1 0 0

gen_edn_if_asserts[1].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 143886 0 0
T2 2200 1117 0 0
T3 3250 0 0 0
T4 7434 0 0 0
T5 0 632 0 0
T6 0 600 0 0
T8 3371 0 0 0
T11 3497 0 0 0
T12 0 7463 0 0
T13 0 230 0 0
T19 2526 0 0 0
T20 5691 0 0 0
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T31 0 31 0 0
T33 0 17 0 0
T34 0 592 0 0
T65 0 248 0 0
T66 0 380 0 0

gen_edn_if_asserts[2].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 477225 0 300
T1 1057 40 0 0
T2 2200 1019 0 0
T3 3250 1721 0 2
T4 7434 865 0 0
T8 3371 90 0 0
T12 0 0 0 2
T18 0 0 0 2
T19 2526 26 0 0
T20 5691 27 0 0
T21 1333 1236 0 2
T22 1860 12 0 0
T23 1578 18 0 0
T40 0 0 0 2
T55 0 0 0 2
T60 0 0 0 2
T61 0 0 0 2
T62 0 0 0 2
T63 0 0 0 2

gen_edn_if_asserts[2].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 4631 0 104
T2 2200 1 0 0
T3 3250 4 0 0
T4 7434 0 0 0
T8 3371 0 0 0
T9 0 3 0 1
T11 3497 0 0 0
T17 0 3 0 1
T19 2526 0 0 0
T20 5691 44 0 1
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T27 0 3 0 1
T42 0 21 0 1
T44 0 3 0 1
T54 0 3 0 1
T57 0 0 0 1
T67 0 0 0 1
T69 0 23 0 1

gen_edn_if_asserts[2].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 143886 0 0
T2 2200 1117 0 0
T3 3250 0 0 0
T4 7434 0 0 0
T5 0 632 0 0
T6 0 600 0 0
T8 3371 0 0 0
T11 3497 0 0 0
T12 0 7463 0 0
T13 0 230 0 0
T19 2526 0 0 0
T20 5691 0 0 0
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T31 0 31 0 0
T33 0 17 0 0
T34 0 592 0 0
T65 0 248 0 0
T66 0 380 0 0

gen_edn_if_asserts[3].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 477225 0 300
T1 1057 40 0 0
T2 2200 1019 0 0
T3 3250 1721 0 2
T4 7434 865 0 0
T8 3371 90 0 0
T12 0 0 0 2
T18 0 0 0 2
T19 2526 26 0 0
T20 5691 27 0 0
T21 1333 1236 0 2
T22 1860 12 0 0
T23 1578 18 0 0
T40 0 0 0 2
T55 0 0 0 2
T60 0 0 0 2
T61 0 0 0 2
T62 0 0 0 2
T63 0 0 0 2

gen_edn_if_asserts[3].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 5352 0 93
T5 1202 0 0 0
T8 3371 0 0 0
T9 0 11 0 1
T11 3497 52 0 1
T17 8524 1191 0 1
T20 5691 57 0 1
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T27 0 3 0 1
T28 2423 0 0 0
T42 0 21 0 1
T43 0 3 0 1
T44 0 3 0 1
T64 1023 0 0 0
T70 0 28 0 1
T71 0 3 0 1

gen_edn_if_asserts[3].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 143886 0 0
T2 2200 1117 0 0
T3 3250 0 0 0
T4 7434 0 0 0
T5 0 632 0 0
T6 0 600 0 0
T8 3371 0 0 0
T11 3497 0 0 0
T12 0 7463 0 0
T13 0 230 0 0
T19 2526 0 0 0
T20 5691 0 0 0
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T31 0 31 0 0
T33 0 17 0 0
T34 0 592 0 0
T65 0 248 0 0
T66 0 380 0 0

gen_edn_if_asserts[4].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 477225 0 300
T1 1057 40 0 0
T2 2200 1019 0 0
T3 3250 1721 0 2
T4 7434 865 0 0
T8 3371 90 0 0
T12 0 0 0 2
T18 0 0 0 2
T19 2526 26 0 0
T20 5691 27 0 0
T21 1333 1236 0 2
T22 1860 12 0 0
T23 1578 18 0 0
T40 0 0 0 2
T55 0 0 0 2
T60 0 0 0 2
T61 0 0 0 2
T62 0 0 0 2
T63 0 0 0 2

gen_edn_if_asserts[4].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 4614 0 101
T1 1057 3 0 1
T2 2200 0 0 0
T3 3250 0 0 0
T4 7434 0 0 0
T8 3371 0 0 0
T9 0 15 0 1
T11 0 3 0 1
T17 0 32 0 1
T19 2526 0 0 0
T20 5691 3 0 1
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T27 0 12 0 1
T42 0 3 0 1
T43 0 41 0 1
T44 0 3 0 1
T57 0 3 0 1

gen_edn_if_asserts[4].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 143886 0 0
T2 2200 1117 0 0
T3 3250 0 0 0
T4 7434 0 0 0
T5 0 632 0 0
T6 0 600 0 0
T8 3371 0 0 0
T11 3497 0 0 0
T12 0 7463 0 0
T13 0 230 0 0
T19 2526 0 0 0
T20 5691 0 0 0
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T31 0 31 0 0
T33 0 17 0 0
T34 0 592 0 0
T65 0 248 0 0
T66 0 380 0 0

gen_edn_if_asserts[5].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 477225 0 300
T1 1057 40 0 0
T2 2200 1019 0 0
T3 3250 1721 0 2
T4 7434 865 0 0
T8 3371 90 0 0
T12 0 0 0 2
T18 0 0 0 2
T19 2526 26 0 0
T20 5691 27 0 0
T21 1333 1236 0 2
T22 1860 12 0 0
T23 1578 18 0 0
T40 0 0 0 2
T55 0 0 0 2
T60 0 0 0 2
T61 0 0 0 2
T62 0 0 0 2
T63 0 0 0 2

gen_edn_if_asserts[5].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 2494 0 78
T5 1202 0 0 0
T8 3371 0 0 0
T11 3497 16 0 1
T17 8524 3 0 1
T20 5691 51 0 1
T21 1333 0 0 0
T22 1860 3 0 1
T23 1578 0 0 0
T28 2423 0 0 0
T42 0 58 0 1
T44 0 3 0 1
T56 0 3 0 1
T64 1023 0 0 0
T67 0 11 0 1
T71 0 0 0 1
T72 0 4 0 0
T73 0 3 0 1

gen_edn_if_asserts[5].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 143886 0 0
T2 2200 1117 0 0
T3 3250 0 0 0
T4 7434 0 0 0
T5 0 632 0 0
T6 0 600 0 0
T8 3371 0 0 0
T11 3497 0 0 0
T12 0 7463 0 0
T13 0 230 0 0
T19 2526 0 0 0
T20 5691 0 0 0
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T31 0 31 0 0
T33 0 17 0 0
T34 0 592 0 0
T65 0 248 0 0
T66 0 380 0 0

gen_edn_if_asserts[6].EdnDataStableDisable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 477225 0 300
T1 1057 40 0 0
T2 2200 1019 0 0
T3 3250 1721 0 2
T4 7434 865 0 0
T8 3371 90 0 0
T12 0 0 0 2
T18 0 0 0 2
T19 2526 26 0 0
T20 5691 27 0 0
T21 1333 1236 0 2
T22 1860 12 0 0
T23 1578 18 0 0
T40 0 0 0 2
T55 0 0 0 2
T60 0 0 0 2
T61 0 0 0 2
T62 0 0 0 2
T63 0 0 0 2

gen_edn_if_asserts[6].EdnDataStable_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 2977 0 76
T5 1202 0 0 0
T8 3371 0 0 0
T11 3497 15 0 1
T17 8524 3 0 1
T20 5691 17 0 1
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T28 2423 0 0 0
T32 0 1 0 0
T42 0 3 0 1
T45 0 3 0 1
T64 1023 0 0 0
T66 0 1 0 0
T71 0 47 0 1
T73 0 20 0 1
T74 0 3 0 1
T75 0 0 0 1
T76 0 0 0 1

gen_edn_if_asserts[6].EdnEndPointOut_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 184847208 0 0
T1 1057 994 0 0
T2 2200 2051 0 0
T3 3250 3192 0 0
T4 7434 7172 0 0
T8 3371 3278 0 0
T19 2526 2463 0 0
T20 5691 5628 0 0
T21 1333 1238 0 0
T22 1860 1767 0 0
T23 1578 1489 0 0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 185001714 143886 0 0
T2 2200 1117 0 0
T3 3250 0 0 0
T4 7434 0 0 0
T5 0 632 0 0
T6 0 600 0 0
T8 3371 0 0 0
T11 3497 0 0 0
T12 0 7463 0 0
T13 0 230 0 0
T19 2526 0 0 0
T20 5691 0 0 0
T21 1333 0 0 0
T22 1860 0 0 0
T23 1578 0 0 0
T31 0 31 0 0
T33 0 17 0 0
T34 0 592 0 0
T65 0 248 0 0
T66 0 380 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%