Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	185495597	8407572	0	0
boot_gen_cmd_rd_A	185495597	45396	0	0
boot_ins_cmd_rd_A	185495597	52782	0	0
ctrl_rd_A	185495597	46196	0	0
err_code_test_rd_A	185495597	52271	0	0
intr_enable_rd_A	185495597	52341	0	0
max_num_reqs_between_reseeds_rd_A	185495597	46606	0	0
regwen_rd_A	185495597	54071	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185495597	8407572	0	0
T10	2428	0	0	0
T39	884402	369017	0	0
T40	188171	111958	0	0
T41	0	154083	0	0
T63	1146	0	0	0
T71	7581	0	0	0
T74	4103	0	0	0
T115	1270	0	0	0
T140	1548	0	0	0
T141	0	368619	0	0
T142	0	390549	0	0
T188	6918	0	0	0
T189	0	141174	0	0
T190	0	368380	0	0
T191	0	47251	0	0
T192	0	68983	0	0
T193	0	281762	0	0
T194	887	0	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185495597	45396	0	0
T51	3734	0	0	0
T81	1179	0	0	0
T88	1186	0	0	0
T150	2424	0	0	0
T177	0	2062	0	0
T192	192800	998	0	0
T195	0	4381	0	0
T196	0	524	0	0
T197	0	4225	0	0
T198	0	7642	0	0
T199	0	2019	0	0
T200	0	6691	0	0
T201	0	1330	0	0
T202	0	5555	0	0
T203	1186	0	0	0
T204	2612	0	0	0
T205	3878	0	0	0
T206	3950	0	0	0
T207	1845	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185495597	52782	0	0
T51	3734	0	0	0
T81	1179	0	0	0
T88	1186	0	0	0
T150	2424	0	0	0
T177	0	2478	0	0
T192	192800	1194	0	0
T195	0	5446	0	0
T196	0	672	0	0
T197	0	4677	0	0
T198	0	8750	0	0
T199	0	2551	0	0
T200	0	7284	0	0
T201	0	1708	0	0
T202	0	6468	0	0
T203	1186	0	0	0
T204	2612	0	0	0
T205	3878	0	0	0
T206	3950	0	0	0
T207	1845	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185495597	46196	0	0
T4	7434	9	0	0
T5	1202	0	0	0
T8	3371	0	0	0
T9	0	4	0	0
T11	3497	0	0	0
T19	2526	0	0	0
T20	5691	0	0	0
T21	1333	0	0	0
T22	1860	0	0	0
T23	1578	0	0	0
T56	0	4	0	0
T64	1023	0	0	0
T177	0	1915	0	0
T192	0	1023	0	0
T195	0	4516	0	0
T196	0	676	0	0
T208	0	1	0	0
T209	0	3	0	0
T210	0	8	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185495597	52271	0	0
T51	3734	0	0	0
T81	1179	0	0	0
T88	1186	0	0	0
T150	2424	0	0	0
T177	0	2507	0	0
T192	192800	1381	0	0
T195	0	5107	0	0
T196	0	691	0	0
T197	0	4908	0	0
T198	0	8759	0	0
T199	0	2519	0	0
T200	0	7258	0	0
T201	0	1523	0	0
T202	0	6034	0	0
T203	1186	0	0	0
T204	2612	0	0	0
T205	3878	0	0	0
T206	3950	0	0	0
T207	1845	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185495597	52341	0	0
T6	2455	0	0	0
T9	2378	0	0	0
T12	24991	0	0	0
T27	3011	0	0	0
T29	1909	0	0	0
T33	603	0	0	0
T44	1804	0	0	0
T47	21856	137	0	0
T65	549	0	0	0
T69	3367	0	0	0
T177	0	2340	0	0
T192	0	1228	0	0
T195	0	4785	0	0
T196	0	825	0	0
T197	0	4180	0	0
T198	0	8230	0	0
T211	0	122	0	0
T212	0	29	0	0
T213	0	33	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185495597	46606	0	0
T51	3734	0	0	0
T81	1179	0	0	0
T88	1186	0	0	0
T150	2424	0	0	0
T177	0	2085	0	0
T192	192800	1082	0	0
T195	0	4395	0	0
T196	0	470	0	0
T197	0	4323	0	0
T198	0	7589	0	0
T199	0	2328	0	0
T200	0	6835	0	0
T201	0	1404	0	0
T202	0	5284	0	0
T203	1186	0	0	0
T204	2612	0	0	0
T205	3878	0	0	0
T206	3950	0	0	0
T207	1845	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	185495597	54071	0	0
T51	3734	0	0	0
T81	1179	0	0	0
T88	1186	0	0	0
T150	2424	0	0	0
T177	0	2415	0	0
T192	192800	1024	0	0
T195	0	5335	0	0
T196	0	614	0	0
T197	0	4743	0	0
T198	0	8604	0	0
T199	0	2549	0	0
T200	0	7489	0	0
T201	0	1652	0	0
T202	0	6442	0	0
T203	1186	0	0	0
T204	2612	0	0	0
T205	3878	0	0	0
T206	3950	0	0	0
T207	1845	0	0	0