Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.51	98.24	93.76	97.01	81.50	96.76	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.46	99.92	92.39	82.54	81.50	99.52	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T26,T27,T28

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T14,T15,T16
1	0	Covered	T4,T6,T13

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1170	1170	100.00
Total Bits 0->1	585	585	100.00
Total Bits 1->0	585	585	100.00

Ports	69	69	100.00
Port Bits	1170	1170	100.00
Port Bits 0->1	585	585	100.00
Port Bits 1->0	585	585	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T3,T18	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T3,T19,T10	Yes	T3,T19,T10	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T36,T37,T38	Yes	T36,T37,T38	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T20	Yes	T1,T2,T19	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
edn_i[1].edn_req	Yes	Yes	T18,T19,T21	Yes	T18,T19,T21	INPUT
edn_i[2].edn_req	Yes	Yes	T18,T21,T39	Yes	T18,T21,T39	INPUT
edn_i[3].edn_req	Yes	Yes	T21,T26,T40	Yes	T21,T26,T40	INPUT
edn_i[4].edn_req	Yes	Yes	T21,T39,T40	Yes	T21,T39,T40	INPUT
edn_i[5].edn_req	Yes	Yes	T21,T31,T41	Yes	T21,T31,T41	INPUT
edn_i[6].edn_req	Yes	Yes	T10,T20,T21	Yes	T10,T20,T21	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T3,T9,T21	Yes	T2,T3,T9	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T18,T19,T21	Yes	T18,T19,T21	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T18,T19,T21	Yes	T18,T19,T21	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T18,T19,T21	Yes	T18,T19,T21	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T18,T21,T39	Yes	T18,T21,T39	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T42,T43,T44	Yes	T18,T39,T45	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T18,T21,T39	Yes	T18,T21,T39	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T21,T40,T45	Yes	T21,T40,T45	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T21,T26,T46	Yes	T21,T26,T46	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T21,T26,T40	Yes	T21,T26,T40	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T21,T39,T40	Yes	T21,T39,T40	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T40,T45,T42	Yes	T21,T40,T47	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T21,T39,T40	Yes	T21,T39,T40	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T21,T41,T48	Yes	T21,T41,T48	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T21,T31,T48	Yes	T21,T31,T48	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T21,T31,T41	Yes	T21,T31,T41	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T10,T20,T39	Yes	T10,T20,T21	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T10,T39,T42	Yes	T10,T20,T21	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T10,T20,T21	Yes	T10,T20,T21	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T2,T3,T9	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T9,T18	Yes	T3,T9,T18	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T9,T18	Yes	T2,T3,T9	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[1:0]	Yes	Yes	T27,T28,T49	Yes	T27,T28,T49	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T50,T51,T26	Yes	T50,T51,T26	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T50,T4,T51	Yes	T50,T4,T51	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T50,T51,T26	Yes	T50,T51,T26	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T50,T4,T51	Yes	T50,T4,T51	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T52,T36	Yes	T5,T52,T36	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T5,T31,T52	Yes	T5,T31,T52	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	193689286	193523675	0	0
CsrngAppIfOut_A	193689286	193523675	0	0
FpvSecCmCntAlertCheck_A	193689286	118	0	0
FpvSecCmGenCmdFifoRptrCheck_A	193689286	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	193689286	70	0	0
FpvSecCmMainFsmCheck_A	193689286	70	0	0
FpvSecCmRegWeOnehotCheck_A	193689286	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	193689286	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	193689286	70	0	0
IntrEdnCmdReqDoneKnownO_A	193689286	193523675	0	0
TlAReadyKnownO_A	193689286	193523675	0	0
TlDValidKnownO_A	193689286	193523675	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	193689286	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	193689286	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	193689286	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	193689286	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	193689286	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	193689286	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	193689286	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	193689286	564509	0	302
gen_edn_if_asserts[0].EdnDataStable_A	193689286	74658	0	348
gen_edn_if_asserts[0].EdnEndPointOut_A	193689286	193523675	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	193689286	154171	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	193689286	564509	0	302
gen_edn_if_asserts[1].EdnDataStable_A	193689286	6609	0	123
gen_edn_if_asserts[1].EdnEndPointOut_A	193689286	193523675	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	193689286	154171	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	193689286	564509	0	302
gen_edn_if_asserts[2].EdnDataStable_A	193689286	5545	0	103
gen_edn_if_asserts[2].EdnEndPointOut_A	193689286	193523675	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	193689286	154171	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	193689286	564509	0	302
gen_edn_if_asserts[3].EdnDataStable_A	193689286	3259	0	93
gen_edn_if_asserts[3].EdnEndPointOut_A	193689286	193523675	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	193689286	154171	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	193689286	564509	0	302
gen_edn_if_asserts[4].EdnDataStable_A	193689286	1989	0	83
gen_edn_if_asserts[4].EdnEndPointOut_A	193689286	193523675	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	193689286	154171	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	193689286	564509	0	302
gen_edn_if_asserts[5].EdnDataStable_A	193689286	2078	0	74
gen_edn_if_asserts[5].EdnEndPointOut_A	193689286	193523675	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	193689286	154171	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	193689286	564509	0	302
gen_edn_if_asserts[6].EdnDataStable_A	193689286	6423	0	90
gen_edn_if_asserts[6].EdnEndPointOut_A	193689286	193523675	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	193689286	154171	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	118	0	0
T4	1565	1	0	0
T5	16511	0	0	0
T6	758	0	0	0
T8	0	1	0	0
T13	842	1	0	0
T14	0	10	0	0
T15	0	20	0	0
T23	1896	0	0	0
T39	5656	0	0	0
T51	1433	0	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	1113	0	0	0
T59	3145	0	0	0
T60	2991	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	70	0	0
T14	24393	10	0	0
T15	0	20	0	0
T16	0	10	0	0
T31	353	0	0	0
T36	185860	0	0	0
T41	2045	0	0	0
T46	1213	0	0	0
T52	32526	0	0	0
T61	0	20	0	0
T62	0	10	0	0
T63	3581	0	0	0
T64	1172	0	0	0
T65	1590	0	0	0
T66	1573	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	564509	0	302
T1	1387	20	0	0
T2	1998	74	0	0
T3	3538	252	0	0
T9	4212	81	0	0
T10	2321	188	0	0
T14	0	0	0	2
T18	2905	31	0	0
T19	1849	139	0	0
T20	638	15	0	0
T21	3775	15	0	0
T22	2122	12	0	0
T38	0	0	0	2
T41	0	0	0	2
T50	0	0	0	2
T51	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	74658	0	348
T1	1387	3	0	1
T2	1998	15	0	1
T3	3538	63	0	1
T5	0	6	0	0
T9	4212	574	0	1
T10	2321	0	0	0
T18	2905	0	0	0
T19	1849	0	0	0
T20	638	0	0	0
T21	3775	13	0	1
T22	2122	8	0	1
T39	0	7	0	1
T58	0	3	0	1
T59	0	0	0	1
T70	0	3	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	154171	0	0
T4	1565	606	0	0
T5	16511	0	0	0
T6	758	360	0	0
T7	0	1072	0	0
T13	842	400	0	0
T14	0	9132	0	0
T23	1896	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T39	5656	0	0	0
T51	1433	0	0	0
T53	0	590	0	0
T58	1113	0	0	0
T59	3145	0	0	0
T60	2991	0	0	0
T71	0	764	0	0
T72	0	496	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	564509	0	302
T1	1387	20	0	0
T2	1998	74	0	0
T3	3538	252	0	0
T9	4212	81	0	0
T10	2321	188	0	0
T14	0	0	0	2
T18	2905	31	0	0
T19	1849	139	0	0
T20	638	15	0	0
T21	3775	15	0	0
T22	2122	12	0	0
T38	0	0	0	2
T41	0	0	0	2
T50	0	0	0	2
T51	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	6609	0	123
T4	1565	0	0	0
T5	16511	0	0	0
T10	2321	0	0	0
T17	0	3	0	1
T18	2905	22	0	1
T19	1849	28	0	1
T20	638	0	0	0
T21	3775	63	0	1
T22	2122	0	0	0
T40	0	31	0	1
T50	2606	0	0	0
T65	0	3	0	1
T66	0	37	0	1
T70	3269	25	0	1
T73	0	4	0	0
T74	0	1009	0	1
T75	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	154171	0	0
T4	1565	606	0	0
T5	16511	0	0	0
T6	758	360	0	0
T7	0	1072	0	0
T13	842	400	0	0
T14	0	9132	0	0
T23	1896	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T39	5656	0	0	0
T51	1433	0	0	0
T53	0	590	0	0
T58	1113	0	0	0
T59	3145	0	0	0
T60	2991	0	0	0
T71	0	764	0	0
T72	0	496	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	564509	0	302
T1	1387	20	0	0
T2	1998	74	0	0
T3	3538	252	0	0
T9	4212	81	0	0
T10	2321	188	0	0
T14	0	0	0	2
T18	2905	31	0	0
T19	1849	139	0	0
T20	638	15	0	0
T21	3775	15	0	0
T22	2122	12	0	0
T38	0	0	0	2
T41	0	0	0	2
T50	0	0	0	2
T51	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	5545	0	103
T4	1565	0	0	0
T5	16511	0	0	0
T10	2321	0	0	0
T18	2905	3	0	1
T19	1849	0	0	0
T20	638	0	0	0
T21	3775	5	0	1
T22	2122	0	0	0
T39	0	3	0	1
T42	0	40	0	1
T43	0	0	0	1
T44	0	0	0	1
T45	0	13	0	1
T48	0	3	0	1
T50	2606	0	0	0
T66	0	3	0	1
T70	3269	0	0	0
T76	0	3	0	1
T77	0	4	0	0
T78	0	4	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	154171	0	0
T4	1565	606	0	0
T5	16511	0	0	0
T6	758	360	0	0
T7	0	1072	0	0
T13	842	400	0	0
T14	0	9132	0	0
T23	1896	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T39	5656	0	0	0
T51	1433	0	0	0
T53	0	590	0	0
T58	1113	0	0	0
T59	3145	0	0	0
T60	2991	0	0	0
T71	0	764	0	0
T72	0	496	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	564509	0	302
T1	1387	20	0	0
T2	1998	74	0	0
T3	3538	252	0	0
T9	4212	81	0	0
T10	2321	188	0	0
T14	0	0	0	2
T18	2905	31	0	0
T19	1849	139	0	0
T20	638	15	0	0
T21	3775	15	0	0
T22	2122	12	0	0
T38	0	0	0	2
T41	0	0	0	2
T50	0	0	0	2
T51	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	3259	0	93
T4	1565	0	0	0
T5	16511	0	0	0
T6	758	0	0	0
T21	3775	11	0	1
T22	2122	0	0	0
T26	0	4	0	0
T28	0	4	0	1
T35	0	1	0	0
T39	5656	0	0	0
T40	0	3	0	1
T44	0	0	0	1
T45	0	40	0	1
T46	0	4	0	0
T50	2606	0	0	0
T51	1433	0	0	0
T58	1113	0	0	0
T70	3269	0	0	0
T75	0	54	0	1
T79	0	51	0	1
T80	0	3	0	1
T81	0	0	0	1
T82	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	154171	0	0
T4	1565	606	0	0
T5	16511	0	0	0
T6	758	360	0	0
T7	0	1072	0	0
T13	842	400	0	0
T14	0	9132	0	0
T23	1896	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T39	5656	0	0	0
T51	1433	0	0	0
T53	0	590	0	0
T58	1113	0	0	0
T59	3145	0	0	0
T60	2991	0	0	0
T71	0	764	0	0
T72	0	496	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	564509	0	302
T1	1387	20	0	0
T2	1998	74	0	0
T3	3538	252	0	0
T9	4212	81	0	0
T10	2321	188	0	0
T14	0	0	0	2
T18	2905	31	0	0
T19	1849	139	0	0
T20	638	15	0	0
T21	3775	15	0	0
T22	2122	12	0	0
T38	0	0	0	2
T41	0	0	0	2
T50	0	0	0	2
T51	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	1989	0	83
T4	1565	0	0	0
T5	16511	0	0	0
T6	758	0	0	0
T21	3775	3	0	1
T22	2122	0	0	0
T33	0	1	0	0
T39	5656	3	0	1
T40	0	39	0	1
T42	0	33	0	1
T45	0	54	0	1
T47	0	3	0	1
T48	0	14	0	1
T49	0	0	0	1
T50	2606	0	0	0
T51	1433	0	0	0
T58	1113	0	0	0
T70	3269	0	0	0
T75	0	3	0	1
T76	0	3	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	154171	0	0
T4	1565	606	0	0
T5	16511	0	0	0
T6	758	360	0	0
T7	0	1072	0	0
T13	842	400	0	0
T14	0	9132	0	0
T23	1896	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T39	5656	0	0	0
T51	1433	0	0	0
T53	0	590	0	0
T58	1113	0	0	0
T59	3145	0	0	0
T60	2991	0	0	0
T71	0	764	0	0
T72	0	496	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	564509	0	302
T1	1387	20	0	0
T2	1998	74	0	0
T3	3538	252	0	0
T9	4212	81	0	0
T10	2321	188	0	0
T14	0	0	0	2
T18	2905	31	0	0
T19	1849	139	0	0
T20	638	15	0	0
T21	3775	15	0	0
T22	2122	12	0	0
T38	0	0	0	2
T41	0	0	0	2
T50	0	0	0	2
T51	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	2078	0	74
T4	1565	0	0	0
T5	16511	0	0	0
T6	758	0	0	0
T11	0	0	0	1
T12	0	0	0	1
T21	3775	17	0	1
T22	2122	0	0	0
T31	0	1	0	0
T39	5656	0	0	0
T41	0	4	0	0
T42	0	69	0	1
T43	0	35	0	1
T44	0	0	0	1
T48	0	35	0	1
T50	2606	0	0	0
T51	1433	0	0	0
T58	1113	0	0	0
T68	0	4	0	0
T70	3269	0	0	0
T80	0	29	0	1
T83	0	4	0	0
T84	0	4	0	0
T85	0	0	0	1
T86	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	154171	0	0
T4	1565	606	0	0
T5	16511	0	0	0
T6	758	360	0	0
T7	0	1072	0	0
T13	842	400	0	0
T14	0	9132	0	0
T23	1896	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T39	5656	0	0	0
T51	1433	0	0	0
T53	0	590	0	0
T58	1113	0	0	0
T59	3145	0	0	0
T60	2991	0	0	0
T71	0	764	0	0
T72	0	496	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	564509	0	302
T1	1387	20	0	0
T2	1998	74	0	0
T3	3538	252	0	0
T9	4212	81	0	0
T10	2321	188	0	0
T14	0	0	0	2
T18	2905	31	0	0
T19	1849	139	0	0
T20	638	15	0	0
T21	3775	15	0	0
T22	2122	12	0	0
T38	0	0	0	2
T41	0	0	0	2
T50	0	0	0	2
T51	0	0	0	2
T60	0	0	0	2
T64	0	0	0	2
T67	0	0	0	2
T68	0	0	0	2
T69	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	6423	0	90
T4	1565	0	0	0
T5	16511	0	0	0
T10	2321	24	0	1
T20	638	3	0	1
T21	3775	3	0	1
T22	2122	0	0	0
T26	0	4	0	1
T39	5656	45	0	1
T42	0	0	0	1
T43	0	0	0	1
T50	2606	0	0	0
T51	1433	0	0	0
T60	0	4	0	0
T70	3269	0	0	0
T71	0	1	0	0
T75	0	3	0	1
T79	0	0	0	1
T87	0	3	0	1
T88	0	1	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	193523675	0	0
T1	1387	1318	0	0
T2	1998	1916	0	0
T3	3538	3471	0	0
T9	4212	4125	0	0
T10	2321	2227	0	0
T18	2905	2842	0	0
T19	1849	1759	0	0
T20	638	556	0	0
T21	3775	3676	0	0
T22	2122	2027	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	193689286	154171	0	0
T4	1565	606	0	0
T5	16511	0	0	0
T6	758	360	0	0
T7	0	1072	0	0
T13	842	400	0	0
T14	0	9132	0	0
T23	1896	0	0	0
T31	0	7	0	0
T32	0	7	0	0
T39	5656	0	0	0
T51	1433	0	0	0
T53	0	590	0	0
T58	1113	0	0	0
T59	3145	0	0	0
T60	2991	0	0	0
T71	0	764	0	0
T72	0	496	0	0