Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	194141086	8874433	0	0
boot_gen_cmd_rd_A	194141086	32539	0	0
boot_ins_cmd_rd_A	194141086	37603	0	0
ctrl_rd_A	194141086	32680	0	0
err_code_test_rd_A	194141086	37988	0	0
intr_enable_rd_A	194141086	38662	0	0
max_num_reqs_between_reseeds_rd_A	194141086	34446	0	0
regwen_rd_A	194141086	38764	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194141086	8874433	0	0
T7	1966	0	0	0
T32	674	0	0	0
T36	185860	105740	0	0
T37	155306	82006	0	0
T38	0	166605	0	0
T45	3782	0	0	0
T47	865	0	0	0
T66	1573	0	0	0
T67	0	55631	0	0
T71	1567	0	0	0
T72	962	0	0	0
T74	7212	0	0	0
T148	0	53483	0	0
T158	0	87734	0	0
T189	0	200585	0	0
T190	0	107622	0	0
T191	0	477845	0	0
T192	0	48769	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194141086	32539	0	0
T24	1597	0	0	0
T48	3088	0	0	0
T67	133656	0	0	0
T68	2075	0	0	0
T148	152064	817	0	0
T158	0	2545	0	0
T193	0	3285	0	0
T194	0	8563	0	0
T195	0	6895	0	0
T196	0	5312	0	0
T197	0	1417	0	0
T198	0	2476	0	0
T199	0	839	0	0
T200	0	21	0	0
T201	2205	0	0	0
T202	19417	0	0	0
T203	8945	0	0	0
T204	1645	0	0	0
T205	1914	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194141086	37603	0	0
T24	1597	0	0	0
T48	3088	0	0	0
T67	133656	0	0	0
T68	2075	0	0	0
T148	152064	1055	0	0
T158	0	3165	0	0
T193	0	3695	0	0
T194	0	9155	0	0
T195	0	7773	0	0
T196	0	6319	0	0
T197	0	1658	0	0
T198	0	3183	0	0
T199	0	1145	0	0
T201	2205	0	0	0
T202	19417	0	0	0
T203	8945	0	0	0
T204	1645	0	0	0
T205	1914	0	0	0
T206	0	5	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194141086	32680	0	0
T7	1966	0	0	0
T35	0	6	0	0
T36	185860	0	0	0
T37	155306	0	0	0
T45	3782	0	0	0
T47	865	0	0	0
T52	32526	4	0	0
T66	1573	0	0	0
T71	1567	0	0	0
T72	962	0	0	0
T74	7212	0	0	0
T84	0	1	0	0
T148	0	863	0	0
T158	0	2520	0	0
T178	0	1	0	0
T193	0	3245	0	0
T194	0	8379	0	0
T207	0	9	0	0
T208	0	1	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194141086	37988	0	0
T24	1597	0	0	0
T48	3088	0	0	0
T67	133656	0	0	0
T68	2075	0	0	0
T148	152064	1055	0	0
T158	0	2876	0	0
T193	0	3786	0	0
T194	0	9843	0	0
T195	0	8121	0	0
T196	0	6220	0	0
T197	0	1540	0	0
T198	0	3156	0	0
T199	0	1031	0	0
T200	0	23	0	0
T201	2205	0	0	0
T202	19417	0	0	0
T203	8945	0	0	0
T204	1645	0	0	0
T205	1914	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194141086	38662	0	0
T7	1966	0	0	0
T36	185860	0	0	0
T37	155306	0	0	0
T45	3782	0	0	0
T47	865	0	0	0
T52	32526	91	0	0
T66	1573	0	0	0
T71	1567	0	0	0
T72	962	0	0	0
T74	7212	0	0	0
T148	0	1065	0	0
T158	0	2759	0	0
T193	0	3858	0	0
T194	0	8746	0	0
T195	0	7750	0	0
T203	0	47	0	0
T207	0	48	0	0
T209	0	84	0	0
T210	0	33	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194141086	34446	0	0
T24	1597	0	0	0
T48	3088	0	0	0
T67	133656	0	0	0
T68	2075	0	0	0
T148	152064	891	0	0
T158	0	2750	0	0
T193	0	3415	0	0
T194	0	8447	0	0
T195	0	6852	0	0
T196	0	5693	0	0
T197	0	1325	0	0
T198	0	2679	0	0
T199	0	885	0	0
T201	2205	0	0	0
T202	19417	0	0	0
T203	8945	0	0	0
T204	1645	0	0	0
T205	1914	0	0	0
T206	0	36	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	194141086	38764	0	0
T24	1597	0	0	0
T48	3088	0	0	0
T67	133656	0	0	0
T68	2075	0	0	0
T148	152064	935	0	0
T158	0	2919	0	0
T193	0	3611	0	0
T194	0	9531	0	0
T195	0	8424	0	0
T196	0	6107	0	0
T197	0	1788	0	0
T198	0	3000	0	0
T199	0	1011	0	0
T201	2205	0	0	0
T202	19417	0	0	0
T203	8945	0	0	0
T204	1645	0	0	0
T205	1914	0	0	0
T206	0	27	0	0