Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.61	98.24	93.76	97.06	82.08	96.76	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.60	99.92	92.39	82.84	82.08	99.52	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T9,T31,T32

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T17,T18,T19
1	0	Covered	T3,T4,T5

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1170	1170	100.00
Total Bits 0->1	585	585	100.00
Total Bits 1->0	585	585	100.00

Ports	69	69	100.00
Port Bits	1170	1170	100.00
Port Bits 0->1	585	585	100.00
Port Bits 1->0	585	585	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T3,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T3,T24	Yes	T1,T3,T24	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T2,T3,T24	Yes	T2,T3,T24	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T3,T24,T4	Yes	T3,T24,T4	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T2,T3,T24	Yes	T2,T3,T24	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T2,*T3,*T24	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T2,T3,T24	Yes	T2,T3,T24	INPUT
edn_i[1].edn_req	Yes	Yes	T1,T2,T27	Yes	T1,T2,T27	INPUT
edn_i[2].edn_req	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	INPUT
edn_i[3].edn_req	Yes	Yes	T27,T43,T44	Yes	T27,T43,T44	INPUT
edn_i[4].edn_req	Yes	Yes	T2,T43,T45	Yes	T2,T43,T45	INPUT
edn_i[5].edn_req	Yes	Yes	T2,T5,T26	Yes	T2,T5,T26	INPUT
edn_i[6].edn_req	Yes	Yes	T25,T43,T46	Yes	T25,T43,T46	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T2,T3,T43	Yes	T2,T3,T24	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T2,T47,T40	Yes	T2,T43,T47	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T2,T3,T24	Yes	T2,T3,T24	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T2,T27,T43	Yes	T1,T2,T27	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T43,T44,T48	Yes	T1,T2,T27	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T1,T2,T27	Yes	T1,T2,T27	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T2,T8,T46	Yes	T2,T8,T46	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T46,T49,T50	Yes	T46,T49,T50	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T2,T4,T8	Yes	T2,T4,T8	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T43,T44,T51	Yes	T27,T43,T44	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T44,T51,T46	Yes	T44,T51,T46	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T27,T43,T44	Yes	T27,T43,T44	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T2,T43,T45	Yes	T2,T43,T45	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T43,T52,T53	Yes	T2,T43,T45	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T2,T43,T45	Yes	T2,T43,T45	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T2,T26,T27	Yes	T2,T26,T27	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T27,T52,T54	Yes	T2,T27,T46	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T2,T26,T27	Yes	T2,T26,T27	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T25,T43,T46	Yes	T25,T43,T46	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T46,T52,T55	Yes	T25,T43,T46	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T25,T43,T46	Yes	T25,T43,T46	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T2,T27,T8	Yes	T2,T27,T8	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T2,T27,T8	Yes	T2,T27,T8	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[1:0]	Yes	Yes	T9,T31,T32	Yes	T9,T31,T32	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T9,T56,T57	Yes	T9,T56,T57	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T9,T56,T57	Yes	T9,T56,T57	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T3,T4,T5	Yes	T3,T4,T5	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T3,T4,T40	Yes	T3,T4,T40	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	224571559	224383159	0	0
CsrngAppIfOut_A	224571559	224383159	0	0
FpvSecCmCntAlertCheck_A	224571559	137	0	0
FpvSecCmGenCmdFifoRptrCheck_A	224571559	90	0	0
FpvSecCmGenCmdFifoWptrCheck_A	224571559	90	0	0
FpvSecCmMainFsmCheck_A	224571559	90	0	0
FpvSecCmRegWeOnehotCheck_A	224571559	90	0	0
FpvSecCmResCmdFifoRptrCheck_A	224571559	90	0	0
FpvSecCmResCmdFifoWptrCheck_A	224571559	90	0	0
IntrEdnCmdReqDoneKnownO_A	224571559	224383159	0	0
TlAReadyKnownO_A	224571559	224383159	0	0
TlDValidKnownO_A	224571559	224383159	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	224571559	90	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	224571559	90	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	224571559	90	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	224571559	90	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	224571559	90	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	224571559	90	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	224571559	90	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	224571559	563740	0	324
gen_edn_if_asserts[0].EdnDataStable_A	224571559	24615	0	337
gen_edn_if_asserts[0].EdnEndPointOut_A	224571559	224383159	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	224571559	170133	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	224571559	563740	0	324
gen_edn_if_asserts[1].EdnDataStable_A	224571559	3213	0	122
gen_edn_if_asserts[1].EdnEndPointOut_A	224571559	224383159	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	224571559	170133	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	224571559	563740	0	324
gen_edn_if_asserts[2].EdnDataStable_A	224571559	4250	0	103
gen_edn_if_asserts[2].EdnEndPointOut_A	224571559	224383159	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	224571559	170133	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	224571559	563740	0	324
gen_edn_if_asserts[3].EdnDataStable_A	224571559	3500	0	97
gen_edn_if_asserts[3].EdnEndPointOut_A	224571559	224383159	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	224571559	170133	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	224571559	563740	0	324
gen_edn_if_asserts[4].EdnDataStable_A	224571559	4323	0	93
gen_edn_if_asserts[4].EdnEndPointOut_A	224571559	224383159	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	224571559	170133	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	224571559	563740	0	324
gen_edn_if_asserts[5].EdnDataStable_A	224571559	51645	0	79
gen_edn_if_asserts[5].EdnEndPointOut_A	224571559	224383159	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	224571559	170133	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	224571559	563740	0	324
gen_edn_if_asserts[6].EdnDataStable_A	224571559	4204	0	75
gen_edn_if_asserts[6].EdnEndPointOut_A	224571559	224383159	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	224571559	170133	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	137	0	0
T7	0	1	0	0
T14	685	1	0	0
T15	0	1	0	0
T16	0	1	0	0
T40	593300	0	0	0
T43	3631	0	0	0
T44	3995	0	0	0
T45	1129	0	0	0
T46	4672	0	0	0
T47	1939	0	0	0
T51	1288	0	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	513	0	0	0
T65	1577	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	90	0	0
T17	46009	20	0	0
T18	0	20	0	0
T19	0	10	0	0
T66	0	20	0	0
T67	0	20	0	0
T68	2712	0	0	0
T69	3020	0	0	0
T70	1604	0	0	0
T71	2366	0	0	0
T72	287756	0	0	0
T73	1819	0	0	0
T74	19525	0	0	0
T75	1710	0	0	0
T76	2023	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	563740	0	324
T1	754	98	0	0
T2	4272	31	0	0
T3	904	398	0	0
T4	855	328	0	0
T5	805	469	0	0
T8	1957	842	0	2
T23	0	0	0	2
T24	1368	20	0	0
T25	1073	79	0	0
T26	848	59	0	0
T27	3218	21	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	24615	0	337
T2	4272	69	0	1
T3	904	1	0	0
T4	855	0	0	0
T5	805	0	0	0
T8	1957	0	0	0
T9	0	0	0	1
T14	685	0	0	0
T24	1368	3	0	1
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	0	0	0
T40	0	127	0	0
T41	0	79	0	0
T43	0	3	0	1
T46	0	3	0	1
T47	0	15	0	1
T49	0	3	0	1
T50	0	0	0	1
T65	0	3	0	1
T80	0	0	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	170133	0	0
T3	904	7	0	0
T4	855	410	0	0
T5	805	186	0	0
T6	0	308	0	0
T8	1957	0	0	0
T14	685	334	0	0
T15	0	604	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	0	0	0
T33	0	22	0	0
T35	0	7	0	0
T43	3631	0	0	0
T64	0	236	0	0
T81	0	481	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	563740	0	324
T1	754	98	0	0
T2	4272	31	0	0
T3	904	398	0	0
T4	855	328	0	0
T5	805	469	0	0
T8	1957	842	0	2
T23	0	0	0	2
T24	1368	20	0	0
T25	1073	79	0	0
T26	848	59	0	0
T27	3218	21	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	3213	0	122
T1	754	3	0	1
T2	4272	3	0	1
T3	904	0	0	0
T4	855	0	0	0
T5	805	0	0	0
T8	1957	0	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	3	0	1
T43	0	35	0	1
T44	0	63	0	1
T46	0	3	0	1
T48	0	58	0	1
T50	0	3	0	1
T52	0	3	0	1
T82	0	37	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	170133	0	0
T3	904	7	0	0
T4	855	410	0	0
T5	805	186	0	0
T6	0	308	0	0
T8	1957	0	0	0
T14	685	334	0	0
T15	0	604	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	0	0	0
T33	0	22	0	0
T35	0	7	0	0
T43	3631	0	0	0
T64	0	236	0	0
T81	0	481	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	563740	0	324
T1	754	98	0	0
T2	4272	31	0	0
T3	904	398	0	0
T4	855	328	0	0
T5	805	469	0	0
T8	1957	842	0	2
T23	0	0	0	2
T24	1368	20	0	0
T25	1073	79	0	0
T26	848	59	0	0
T27	3218	21	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	4250	0	103
T2	4272	3	0	1
T3	904	0	0	0
T4	855	1	0	0
T5	805	0	0	0
T8	1957	4	0	0
T14	685	0	0	0
T20	0	3	0	1
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	0	0	0
T46	0	61	0	1
T49	0	19	0	1
T50	0	60	0	1
T52	0	3	0	1
T53	0	0	0	1
T82	0	13	0	1
T83	0	3	0	1
T84	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	170133	0	0
T3	904	7	0	0
T4	855	410	0	0
T5	805	186	0	0
T6	0	308	0	0
T8	1957	0	0	0
T14	685	334	0	0
T15	0	604	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	0	0	0
T33	0	22	0	0
T35	0	7	0	0
T43	3631	0	0	0
T64	0	236	0	0
T81	0	481	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	563740	0	324
T1	754	98	0	0
T2	4272	31	0	0
T3	904	398	0	0
T4	855	328	0	0
T5	805	469	0	0
T8	1957	842	0	2
T23	0	0	0	2
T24	1368	20	0	0
T25	1073	79	0	0
T26	848	59	0	0
T27	3218	21	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	3500	0	97
T8	1957	0	0	0
T14	685	0	0	0
T27	3218	3	0	1
T40	593300	0	0	0
T43	3631	3	0	1
T44	3995	43	0	1
T45	1129	0	0	0
T46	0	10	0	1
T47	1939	0	0	0
T49	0	13	0	1
T50	0	23	0	1
T51	1288	4	0	0
T53	0	3	0	1
T64	513	0	0	0
T85	0	19	0	1
T86	0	3	0	1
T87	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	170133	0	0
T3	904	7	0	0
T4	855	410	0	0
T5	805	186	0	0
T6	0	308	0	0
T8	1957	0	0	0
T14	685	334	0	0
T15	0	604	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	0	0	0
T33	0	22	0	0
T35	0	7	0	0
T43	3631	0	0	0
T64	0	236	0	0
T81	0	481	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	563740	0	324
T1	754	98	0	0
T2	4272	31	0	0
T3	904	398	0	0
T4	855	328	0	0
T5	805	469	0	0
T8	1957	842	0	2
T23	0	0	0	2
T24	1368	20	0	0
T25	1073	79	0	0
T26	848	59	0	0
T27	3218	21	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	4323	0	93
T2	4272	3	0	1
T3	904	0	0	0
T4	855	0	0	0
T5	805	0	0	0
T8	1957	0	0	0
T14	685	0	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	0	0	0
T43	0	17	0	1
T45	0	3	0	1
T46	0	11	0	1
T50	0	3	0	1
T52	0	58	0	1
T53	0	55	0	1
T87	0	31	0	1
T88	0	4	0	1
T89	0	49	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	170133	0	0
T3	904	7	0	0
T4	855	410	0	0
T5	805	186	0	0
T6	0	308	0	0
T8	1957	0	0	0
T14	685	334	0	0
T15	0	604	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	0	0	0
T33	0	22	0	0
T35	0	7	0	0
T43	3631	0	0	0
T64	0	236	0	0
T81	0	481	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	563740	0	324
T1	754	98	0	0
T2	4272	31	0	0
T3	904	398	0	0
T4	855	328	0	0
T5	805	469	0	0
T8	1957	842	0	2
T23	0	0	0	2
T24	1368	20	0	0
T25	1073	79	0	0
T26	848	59	0	0
T27	3218	21	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	51645	0	79
T2	4272	3	0	1
T3	904	0	0	0
T4	855	0	0	0
T5	805	0	0	0
T8	1957	0	0	0
T14	685	0	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	3	0	1
T27	3218	21	0	1
T43	0	3	0	1
T46	0	3	0	1
T50	0	3	0	1
T52	0	43	0	1
T53	0	3	0	1
T83	0	7	0	1
T90	0	3	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	170133	0	0
T3	904	7	0	0
T4	855	410	0	0
T5	805	186	0	0
T6	0	308	0	0
T8	1957	0	0	0
T14	685	334	0	0
T15	0	604	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	0	0	0
T33	0	22	0	0
T35	0	7	0	0
T43	3631	0	0	0
T64	0	236	0	0
T81	0	481	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	563740	0	324
T1	754	98	0	0
T2	4272	31	0	0
T3	904	398	0	0
T4	855	328	0	0
T5	805	469	0	0
T8	1957	842	0	2
T23	0	0	0	2
T24	1368	20	0	0
T25	1073	79	0	0
T26	848	59	0	0
T27	3218	21	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T56	0	0	0	2
T57	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	4204	0	75
T5	805	0	0	0
T8	1957	0	0	0
T10	0	3	0	1
T14	685	0	0	0
T25	1073	3	0	1
T26	848	0	0	0
T27	3218	0	0	0
T40	593300	0	0	0
T43	3631	12	0	1
T45	1129	0	0	0
T46	0	58	0	1
T47	1939	0	0	0
T50	0	6	0	1
T52	0	39	0	1
T85	0	3	0	1
T89	0	3	0	1
T91	0	3	0	1
T92	0	3	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	224383159	0	0
T1	754	680	0	0
T2	4272	4220	0	0
T3	904	757	0	0
T4	855	728	0	0
T5	805	638	0	0
T8	1957	1894	0	0
T24	1368	1293	0	0
T25	1073	992	0	0
T26	848	776	0	0
T27	3218	3126	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	224571559	170133	0	0
T3	904	7	0	0
T4	855	410	0	0
T5	805	186	0	0
T6	0	308	0	0
T8	1957	0	0	0
T14	685	334	0	0
T15	0	604	0	0
T24	1368	0	0	0
T25	1073	0	0	0
T26	848	0	0	0
T27	3218	0	0	0
T33	0	22	0	0
T35	0	7	0	0
T43	3631	0	0	0
T64	0	236	0	0
T81	0	481	0	0