Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	225107955	10507981	0	0
boot_gen_cmd_rd_A	225107955	56143	0	0
boot_ins_cmd_rd_A	225107955	64084	0	0
ctrl_rd_A	225107955	55864	0	0
err_code_test_rd_A	225107955	63822	0	0
intr_enable_rd_A	225107955	62435	0	0
max_num_reqs_between_reseeds_rd_A	225107955	56508	0	0
regwen_rd_A	225107955	64297	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225107955	10507981	0	0
T9	1820	0	0	0
T40	593300	328558	0	0
T41	563349	190783	0	0
T42	0	18723	0	0
T44	3995	0	0	0
T45	1129	0	0	0
T46	4672	0	0	0
T49	2198	0	0	0
T51	1288	0	0	0
T64	513	0	0	0
T65	1577	0	0	0
T79	0	86490	0	0
T165	0	138349	0	0
T200	0	287872	0	0
T201	0	117167	0	0
T202	0	435268	0	0
T203	0	108693	0	0
T204	0	13716	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225107955	56143	0	0
T9	1820	0	0	0
T15	1061	0	0	0
T41	563349	5675	0	0
T42	471595	266	0	0
T50	2256	0	0	0
T56	1123	0	0	0
T57	1130	0	0	0
T79	0	2629	0	0
T80	1831	0	0	0
T138	962	0	0	0
T163	18435	0	0	0
T200	0	8085	0	0
T203	0	3154	0	0
T205	0	6897	0	0
T206	0	6408	0	0
T207	0	3803	0	0
T208	0	8755	0	0
T209	0	949	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225107955	64084	0	0
T9	1820	0	0	0
T15	1061	0	0	0
T41	563349	6501	0	0
T42	471595	301	0	0
T50	2256	0	0	0
T56	1123	0	0	0
T57	1130	0	0	0
T79	0	2830	0	0
T80	1831	0	0	0
T138	962	0	0	0
T163	18435	0	0	0
T200	0	9374	0	0
T203	0	4034	0	0
T205	0	7228	0	0
T206	0	7595	0	0
T207	0	4476	0	0
T208	0	10281	0	0
T209	0	933	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225107955	55864	0	0
T9	1820	0	0	0
T15	1061	0	0	0
T28	0	5	0	0
T41	563349	5354	0	0
T42	471595	330	0	0
T50	2256	0	0	0
T56	1123	0	0	0
T57	1130	0	0	0
T79	0	2567	0	0
T80	1831	0	0	0
T120	0	5	0	0
T138	962	5	0	0
T163	18435	0	0	0
T200	0	8435	0	0
T203	0	3124	0	0
T205	0	6661	0	0
T210	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225107955	63822	0	0
T9	1820	0	0	0
T15	1061	0	0	0
T41	563349	5957	0	0
T42	471595	364	0	0
T50	2256	0	0	0
T56	1123	0	0	0
T57	1130	0	0	0
T79	0	3016	0	0
T80	1831	0	0	0
T138	962	0	0	0
T163	18435	0	0	0
T200	0	9516	0	0
T203	0	3636	0	0
T205	0	7485	0	0
T206	0	7477	0	0
T207	0	4340	0	0
T208	0	10107	0	0
T209	0	1054	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225107955	62435	0	0
T9	1820	0	0	0
T15	1061	0	0	0
T41	563349	6080	0	0
T42	471595	326	0	0
T50	2256	0	0	0
T56	1123	0	0	0
T57	1130	0	0	0
T78	0	31	0	0
T79	0	3092	0	0
T80	1831	0	0	0
T138	962	0	0	0
T163	18435	55	0	0
T200	0	8373	0	0
T203	0	3363	0	0
T205	0	6821	0	0
T211	0	16	0	0
T212	0	10	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225107955	56508	0	0
T9	1820	0	0	0
T15	1061	0	0	0
T41	563349	5372	0	0
T42	471595	294	0	0
T50	2256	0	0	0
T56	1123	0	0	0
T57	1130	0	0	0
T79	0	2648	0	0
T80	1831	0	0	0
T138	962	0	0	0
T163	18435	0	0	0
T200	0	8290	0	0
T203	0	3252	0	0
T205	0	6918	0	0
T206	0	6359	0	0
T207	0	3911	0	0
T208	0	8617	0	0
T209	0	868	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	225107955	64297	0	0
T9	1820	0	0	0
T15	1061	0	0	0
T41	563349	6152	0	0
T42	471595	328	0	0
T50	2256	0	0	0
T56	1123	0	0	0
T57	1130	0	0	0
T79	0	3081	0	0
T80	1831	0	0	0
T138	962	0	0	0
T163	18435	0	0	0
T200	0	9520	0	0
T203	0	3647	0	0
T205	0	7141	0	0
T206	0	7669	0	0
T207	0	4268	0	0
T208	0	9717	0	0
T209	0	1125	0	0