Group : tb.dut.u_edn_cov_if::edn_cfg_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : tb.dut.u_edn_cov_if::edn_cfg_cg
SCOREINSTANCESWEIGHTGOALAT LEASTPER INSTANCEAUTO BIN MAXPRINT MISSING
100.00 100.00 1 100 1 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_edn_cov_0/edn_cov_if.sv

1 Instances:
NAMESCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
edn_cfg_cg 100.00 1 100 1 64 64




Group Instance : edn_cfg_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64




Summary for Group Instance edn_cfg_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00
Crosses 21 0 21 100.00


Variables for Group Instance edn_cfg_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_mode 3 0 3 100.00 100 1 1 0
cp_num_boot_reqs 2 0 2 100.00 100 1 1 0
cp_num_endpoints 7 0 7 100.00 100 1 1 8


Crosses for Group Instance edn_cfg_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
cr_num_endpoints_mode 21 0 21 100.00 100 1 1 0


Summary for Variable cp_mode

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_mode

Excluded/Illegal bins
NAMECOUNTSTATUS
both 0 Illegal


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
boot_req_mode 147 1 T19 1 T20 1 T37 1
auto_req_mode 131 1 T3 1 T8 1 T9 1
sw_mode 3137 1 T18 1 T54 1 T21 1



Summary for Variable cp_num_boot_reqs

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 2 0 2 100.00


User Defined Bins for cp_num_boot_reqs

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
multiple 294 1 T3 1 T18 1 T20 1
single 100 1 T19 1 T37 1 T83 1



Summary for Variable cp_num_endpoints

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 7 0 7 100.00


Automatically Generated Bins for cp_num_endpoints

Excluded/Illegal bins
NAMECOUNTSTATUS
zero 0 Excluded
[auto[0]] 0 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] 1322 1 T3 1 T18 1 T19 1
auto[2] 123 1 T37 1 T9 1 T48 7
auto[3] 191 1 T78 1 T271 1 T158 9
auto[4] 67 1 T42 1 T87 1 T272 1
auto[5] 207 1 T38 1 T213 1 T273 1
auto[6] 91 1 T10 1 T76 1 T49 6
auto[7] 1414 1 T40 1 T39 1 T44 1



Summary for Cross cr_num_endpoints_mode

Samples crossed: cp_num_endpoints cp_mode
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 21 0 21 100.00


Automatically Generated Cross Bins for cr_num_endpoints_mode

Excluded/Illegal bins
cp_num_endpointscp_modeCOUNTSTATUS
[auto[0]] [boot_req_mode , auto_req_mode , sw_mode] -- Excluded (3 bins)


Covered bins
cp_num_endpointscp_modeCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[1] boot_req_mode 88 1 T19 1 T20 1 T73 1
auto[1] auto_req_mode 73 1 T3 1 T8 1 T45 1
auto[1] sw_mode 1161 1 T18 1 T54 1 T21 1
auto[2] boot_req_mode 7 1 T37 1 T274 1 T275 1
auto[2] auto_req_mode 9 1 T9 1 T276 1 T277 1
auto[2] sw_mode 107 1 T48 7 T156 4 T58 17
auto[3] boot_req_mode 8 1 T78 1 T278 1 T279 1
auto[3] auto_req_mode 7 1 T280 1 T281 1 T282 1
auto[3] sw_mode 176 1 T271 1 T158 9 T35 17
auto[4] boot_req_mode 3 1 T42 1 T283 1 T284 1
auto[4] auto_req_mode 4 1 T272 1 T285 1 T286 1
auto[4] sw_mode 60 1 T87 1 T171 1 T287 30
auto[5] boot_req_mode 4 1 T213 1 T288 1 T289 1
auto[5] auto_req_mode 4 1 T273 1 T290 1 T291 1
auto[5] sw_mode 199 1 T38 1 T292 1 T293 1
auto[6] boot_req_mode 4 1 T82 1 T294 1 T295 1
auto[6] auto_req_mode 5 1 T10 1 T76 1 T296 1
auto[6] sw_mode 82 1 T49 6 T214 4 T297 1
auto[7] boot_req_mode 33 1 T39 1 T86 1 T77 1
auto[7] auto_req_mode 29 1 T41 1 T298 1 T11 1
auto[7] sw_mode 1352 1 T40 1 T44 1 T90 1

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