SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING |
63.64 | 63.64 | 1 | 100 | 1 | 1 | 64 | 64 |
NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
edn_sw_cmd_sts_cg | 63.64 | 1 | 100 | 1 | 64 | 64 |
SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
63.64 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 11 | 4 | 7 | 63.64 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
cp_cmd_ack_cg | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_cmd_rdy_cg | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_cmd_reg_rdy_cg | 2 | 0 | 2 | 100.00 | 100 | 1 | 1 | 0 | |
cp_cmd_sts_cg | 5 | 4 | 1 | 20.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
no_ack | 28865 | 1 | T3 | 17 | T18 | 26 | T19 | 23 | ||||
ack | 23493 | 1 | T3 | 2 | T18 | 9 | T19 | 7 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
not_ready | 27973 | 1 | T3 | 17 | T18 | 25 | T19 | 22 | ||||
ready | 24385 | 1 | T3 | 2 | T18 | 10 | T19 | 8 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins | 2 | 0 | 2 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
not_ready | 491 | 1 | T3 | 2 | T8 | 2 | T9 | 1 | ||||
ready | 51867 | 1 | T3 | 17 | T18 | 35 | T19 | 30 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 5 | 4 | 1 | 20.00 |
NAME | COUNT | AT LEAST | NUMBER | STATUS |
auto[CMD_STS_INVALID_ACMD] | 0 | 1 | 1 | |
auto[CMD_STS_INVALID_GEN_CMD] | 0 | 1 | 1 | |
auto[CMD_STS_INVALID_CMD_SEQ] | 0 | 1 | 1 | |
auto[CMD_STS_UNDRIVEN] | 0 | 1 | 1 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[CMD_STS_SUCCESS] | 52358 | 1 | T3 | 19 | T18 | 35 | T19 | 30 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |