Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_edn_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	721303	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

5866783

1

T1

7

T2

6

T3

74

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1739283	1			T1	4		T2	4		T3	29
values[0x0]	2241808	1			T1	6		T2	3		T3	43
values[0x1]	2606995	1			T1	4		T2	5		T3	37

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	354501	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

6233585

1

T1

7

T2

6

T3

84

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	26791	1			T20	2		T8	1		T50	1
valid_sources[0x01]	24625	1			T96	2		T48	2		T76	10
valid_sources[0x02]	25833	1			T50	1		T72	1		T38	2
valid_sources[0x03]	26587	1			T18	4		T21	1		T73	1
valid_sources[0x04]	25728	1			T50	1		T73	2		T38	1
valid_sources[0x05]	25833	1			T54	5		T73	2		T45	1
valid_sources[0x06]	24529	1			T21	1		T9	1		T38	2
valid_sources[0x07]	26885	1			T18	2		T20	4		T8	1
valid_sources[0x08]	25506	1			T21	1		T73	1		T42	1
valid_sources[0x09]	25176	1			T8	4		T9	2		T73	1
valid_sources[0x0a]	23744	1			T13	2		T50	2		T24	1
valid_sources[0x0b]	25331	1			T21	1		T44	1		T47	4
valid_sources[0x0c]	24610	1			T54	2		T85	2		T300	1
valid_sources[0x0d]	25835	1			T18	1		T8	4		T38	1
valid_sources[0x0e]	25555	1			T38	1		T39	4		T75	2
valid_sources[0x0f]	26305	1			T38	1		T42	3		T45	1
valid_sources[0x10]	24321	1			T18	1		T13	1		T38	2
valid_sources[0x11]	25632	1			T38	3		T42	2		T47	8
valid_sources[0x12]	24541	1			T73	1		T39	5		T160	1
valid_sources[0x13]	25982	1			T50	1		T72	1		T9	1
valid_sources[0x14]	25659	1			T39	3		T47	2		T151	4
valid_sources[0x15]	25330	1			T21	1		T38	1		T300	3
valid_sources[0x16]	24914	1			T24	1		T25	1		T26	1
valid_sources[0x17]	24431	1			T50	1		T9	1		T73	2
valid_sources[0x18]	25340	1			T85	3		T26	2		T300	2
valid_sources[0x19]	25374	1			T20	3		T50	1		T72	1
valid_sources[0x1a]	25406	1			T9	2		T24	1		T45	1
valid_sources[0x1b]	24927	1			T21	1		T38	1		T26	1
valid_sources[0x1c]	26019	1			T72	1		T38	1		T42	3
valid_sources[0x1d]	26380	1			T20	2		T21	1		T73	1
valid_sources[0x1e]	27786	1			T18	1		T8	1		T21	1
valid_sources[0x1f]	26243	1			T20	2		T50	1		T73	2
valid_sources[0x20]	26545	1			T38	1		T25	1		T47	10
valid_sources[0x21]	27771	1			T8	5		T10	7		T92	1
valid_sources[0x22]	28085	1			T50	1		T54	1		T73	2
valid_sources[0x23]	26356	1			T20	4		T8	3		T54	5
valid_sources[0x24]	26294	1			T9	2		T39	2		T26	1
valid_sources[0x25]	25441	1			T8	1		T50	1		T73	1
valid_sources[0x26]	25787	1			T20	1		T9	2		T38	1
valid_sources[0x27]	26024	1			T9	1		T38	1		T25	1
valid_sources[0x28]	26141	1			T9	1		T85	1		T25	2
valid_sources[0x29]	25582	1			T39	7		T96	5		T160	2
valid_sources[0x2a]	24123	1			T20	1		T73	1		T38	1
valid_sources[0x2b]	23115	1			T18	1		T9	1		T45	1
valid_sources[0x2c]	25226	1			T8	3		T9	2		T73	1
valid_sources[0x2d]	27747	1			T20	1		T51	1		T39	1
valid_sources[0x2e]	27434	1			T39	1		T44	2		T47	7
valid_sources[0x2f]	25818	1			T8	3		T73	2		T38	1
valid_sources[0x30]	26770	1			T45	1		T300	1		T158	2
valid_sources[0x31]	27469	1			T9	2		T38	1		T42	2
valid_sources[0x32]	25737	1			T50	1		T73	1		T38	1
valid_sources[0x33]	26627	1			T4	29		T18	4		T8	2
valid_sources[0x34]	25844	1			T18	2		T24	2		T25	9
valid_sources[0x35]	24615	1			T13	2		T42	1		T24	1
valid_sources[0x36]	27765	1			T20	3		T50	1		T73	1
valid_sources[0x37]	27122	1			T18	1		T45	1		T96	1
valid_sources[0x38]	26935	1			T18	3		T50	1		T85	1
valid_sources[0x39]	27116	1			T18	1		T50	1		T9	1
valid_sources[0x3a]	23214	1			T72	1		T10	5		T39	6
valid_sources[0x3b]	26041	1			T38	1		T45	1		T26	1
valid_sources[0x3c]	24708	1			T73	1		T42	1		T24	5
valid_sources[0x3d]	25283	1			T50	1		T72	2		T39	4
valid_sources[0x3e]	26860	1			T38	1		T85	1		T44	1
valid_sources[0x3f]	25882	1			T13	3		T73	1		T38	1
valid_sources[0x40]	25382	1			T8	2		T72	3		T9	2
valid_sources[0x41]	28419	1			T50	1		T73	1		T45	1
valid_sources[0x42]	25458	1			T39	3		T301	1		T47	4
valid_sources[0x43]	24223	1			T21	1		T73	1		T38	1
valid_sources[0x44]	24211	1			T38	1		T42	2		T47	3
valid_sources[0x45]	26957	1			T18	5		T8	3		T72	2
valid_sources[0x46]	25674	1			T85	1		T25	3		T39	7
valid_sources[0x47]	25288	1			T18	1		T38	3		T39	2
valid_sources[0x48]	26187	1			T20	4		T50	1		T24	3
valid_sources[0x49]	26233	1			T38	1		T39	1		T44	1
valid_sources[0x4a]	25498	1			T50	1		T72	1		T38	1
valid_sources[0x4b]	26048	1			T18	4		T45	1		T85	1
valid_sources[0x4c]	24624	1			T50	2		T26	1		T28	1
valid_sources[0x4d]	25713	1			T85	1		T39	5		T28	2
valid_sources[0x4e]	26983	1			T18	1		T8	2		T24	2
valid_sources[0x4f]	25723	1			T20	1		T8	1		T72	1
valid_sources[0x50]	26692	1			T21	1		T9	1		T45	2
valid_sources[0x51]	25974	1			T9	1		T38	1		T44	1
valid_sources[0x52]	25751	1			T18	1		T73	1		T10	6
valid_sources[0x53]	26143	1			T20	1		T8	3		T21	2
valid_sources[0x54]	26687	1			T18	2		T24	3		T45	1
valid_sources[0x55]	27952	1			T21	1		T73	1		T38	3
valid_sources[0x56]	25676	1			T73	1		T38	1		T85	1
valid_sources[0x57]	28465	1			T8	1		T50	2		T38	1
valid_sources[0x58]	24310	1			T18	4		T54	2		T9	1
valid_sources[0x59]	25449	1			T18	1		T8	2		T9	1
valid_sources[0x5a]	24901	1			T73	1		T42	2		T85	1
valid_sources[0x5b]	25897	1			T21	1		T85	1		T25	4
valid_sources[0x5c]	23404	1			T85	2		T26	1		T44	1
valid_sources[0x5d]	24841	1			T26	1		T160	1		T155	1
valid_sources[0x5e]	26509	1			T13	3		T72	2		T38	2
valid_sources[0x5f]	25717	1			T20	7		T38	1		T44	2
valid_sources[0x60]	26091	1			T8	1		T50	2		T25	2
valid_sources[0x61]	25528	1			T18	2		T20	2		T21	1
valid_sources[0x62]	26847	1			T18	1		T50	1		T38	3
valid_sources[0x63]	26864	1			T38	1		T86	1		T47	4
valid_sources[0x64]	25203	1			T21	2		T42	5		T39	2
valid_sources[0x65]	24997	1			T38	1		T26	1		T160	1
valid_sources[0x66]	24100	1			T18	2		T9	1		T47	1
valid_sources[0x67]	25010	1			T20	2		T92	3		T158	1
valid_sources[0x68]	27351	1			T20	3		T21	1		T9	1
valid_sources[0x69]	25048	1			T10	1		T44	2		T92	2
valid_sources[0x6a]	25670	1			T74	17		T26	2		T155	1
valid_sources[0x6b]	25647	1			T50	1		T38	1		T47	4
valid_sources[0x6c]	22486	1			T9	2		T73	1		T155	1
valid_sources[0x6d]	24492	1			T38	1		T85	1		T26	1
valid_sources[0x6e]	26097	1			T18	4		T50	1		T38	1
valid_sources[0x6f]	26201	1			T73	1		T45	2		T85	2
valid_sources[0x70]	26801	1			T20	5		T38	1		T42	3
valid_sources[0x71]	25709	1			T8	2		T21	1		T73	1
valid_sources[0x72]	25625	1			T44	1		T47	6		T87	2
valid_sources[0x73]	24628	1			T22	1		T24	2		T85	1
valid_sources[0x74]	26483	1			T20	1		T8	7		T22	1
valid_sources[0x75]	26104	1			T8	3		T22	3		T85	1
valid_sources[0x76]	26180	1			T10	21		T39	5		T155	3
valid_sources[0x77]	27136	1			T50	1		T22	2		T85	1
valid_sources[0x78]	24933	1			T18	2		T50	1		T85	1
valid_sources[0x79]	27502	1			T24	5		T39	4		T44	1
valid_sources[0x7a]	24937	1			T9	2		T45	1		T25	1
valid_sources[0x7b]	26608	1			T8	3		T21	1		T38	1
valid_sources[0x7c]	26318	1			T18	1		T9	1		T45	1
valid_sources[0x7d]	25259	1			T18	1		T45	1		T44	1
valid_sources[0x7e]	24740	1			T21	1		T38	3		T90	3
valid_sources[0x7f]	26557	1			T9	2		T24	1		T45	1
valid_sources[0x80]	26732	1			T20	1		T9	1		T24	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

1476422

1

T1

2

T2

2

T3

3

values[0x0]

all_enables

biggest_size

2196724

1

T1

3

T2

2

T3

37

values[0x1]

all_enables

biggest_size

2193637

1

T1

2

T2

2

T3

34