Unified Coverage Report :: Group :: csrng_agent_pkg::device_cmd_cg

Group : csrng_agent_pkg::device_cmd_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
65.62	65.62	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_csrng_agent_0.1/csrng_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
csrng_agent_pkg.csrng_device_cmd_cg	65.62	1	100	1	64	64

---

Group Instance : csrng_agent_pkg.csrng_device_cmd_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
65.62	1	100	1	64	64

---

Summary for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	52	22	30	57.69

Variables for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
csrng_clen_cp	3	0	3	100.00	100	1	1	0
csrng_cmd_cp	5	0	5	100.00	100	1	1	0
csrng_flag_cp	2	0	2	100.00	100	1	1	0
csrng_sts	2	0	2	100.00	100	1	1	0

Crosses for Group Instance csrng_agent_pkg.csrng_device_cmd_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
csrng_cmd_cross	52	22	30	57.69	100	1	1	0

Summary for Variable csrng_clen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for csrng_clen_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
non_zero_bins[0]	2824	1			T3	6		T8	4		T37	2
non_zero_bins[1]	1894	1			T3	4		T18	3		T19	2
zero	8967	1			T4	2		T18	2		T19	5

---

Summary for Variable csrng_cmd_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for csrng_cmd_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	522	1			T19	1		T73	1		T84	1
uni	3854	1			T18	2		T19	2		T20	3
gen	4118	1			T3	3		T4	1		T18	1
res	820	1			T3	5		T8	3		T9	2
ins	4371	1			T3	2		T4	1		T18	2

---

Summary for Variable csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_flag_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

mubi_false

9327

1

T3

2

T4

2

T18

4

mubi_true

4358

1

T3

8

T18

1

T19

2

---

Summary for Variable csrng_sts

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for csrng_sts

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

fail

32

1

T24

1

T25

1

T26

1

pass

13653

1

T3

10

T4

2

T18

5

---

Summary for Cross csrng_cmd_cross

Samples crossed: csrng_cmd_cp csrng_clen_cp csrng_sts csrng_flag_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	52	22	30	57.69	22
Automatically Generated Cross Bins	52	22	30	57.69	22
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for csrng_cmd_cross

Element holes

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[upd]	*	[fail]	*	--	--	6
[gen , res , ins]	[non_zero_bins[0] , non_zero_bins[1]]	[fail]	*	--	--	12

Uncovered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	NUMBER	STATUS
[uni]	[zero]	[fail]	[mubi_true]	0	1	1
[gen , res , ins]	[zero]	[fail]	[mubi_true]	--	--	3

Covered bins

csrng_cmd_cp	csrng_clen_cp	csrng_sts	csrng_flag_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
upd	non_zero_bins[0]	pass	mubi_false	120	1			T48	1		T34	4		T35	1
upd	non_zero_bins[0]	pass	mubi_true	129	1			T73	1		T44	1		T47	1
upd	non_zero_bins[1]	pass	mubi_false	84	1			T84	1		T86	1		T47	1
upd	non_zero_bins[1]	pass	mubi_true	86	1			T90	1		T48	1		T34	2
upd	zero	pass	mubi_false	50	1			T19	1		T34	2		T35	1
upd	zero	pass	mubi_true	53	1			T34	1		T36	1		T195	1
uni	zero	fail	mubi_false	4	1			T93	1		T149	1		T246	1
uni	zero	pass	mubi_false	2782	1			T18	2		T19	2		T20	3
uni	zero	pass	mubi_true	1068	1			T54	1		T71	1		T37	1
gen	non_zero_bins[0]	pass	mubi_false	502	1			T84	1		T92	2		T96	3
gen	non_zero_bins[0]	pass	mubi_true	545	1			T3	3		T37	1		T73	1
gen	non_zero_bins[1]	pass	mubi_false	368	1			T19	1		T20	1		T8	3
gen	non_zero_bins[1]	pass	mubi_true	328	1			T18	1		T10	5		T160	1
gen	zero	fail	mubi_false	11	1			T161	1		T163	1		T247	1
gen	zero	pass	mubi_false	1956	1			T4	1		T19	1		T14	2
gen	zero	pass	mubi_true	408	1			T13	2		T37	1		T83	1
res	non_zero_bins[0]	pass	mubi_false	209	1			T45	1		T34	4		T36	3
res	non_zero_bins[0]	pass	mubi_true	195	1			T3	2		T8	2		T76	2
res	non_zero_bins[1]	pass	mubi_false	136	1			T9	2		T96	2		T160	1
res	non_zero_bins[1]	pass	mubi_true	98	1			T3	3		T8	1		T10	2
res	zero	fail	mubi_false	10	1			T24	1		T91	1		T89	1
res	zero	pass	mubi_false	84	1			T85	2		T92	2		T41	2
res	zero	pass	mubi_true	88	1			T34	2		T36	1		T195	2
ins	non_zero_bins[0]	pass	mubi_false	583	1			T3	1		T8	1		T9	1
ins	non_zero_bins[0]	pass	mubi_true	541	1			T8	1		T37	1		T38	1
ins	non_zero_bins[1]	pass	mubi_false	388	1			T3	1		T18	2		T83	1
ins	non_zero_bins[1]	pass	mubi_true	406	1			T19	1		T37	1		T73	1
ins	zero	fail	mubi_false	7	1			T25	1		T26	1		T248	1
ins	zero	pass	mubi_false	2033	1			T4	1		T13	1		T14	1
ins	zero	pass	mubi_true	413	1			T19	1		T13	1		T14	1

User Defined Cross Bins for csrng_cmd_cross

Excluded/Illegal bins

NAME	COUNT	STATUS
uni_clen	0	Excluded