Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_edn_core.u_prim_fifo_sync_rescmd	94.64	100.00	78.57			100.00	100.00
tb.dut.u_edn_core.u_prim_fifo_sync_gencmd	94.64	100.00	78.57			100.00	100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

---

Module Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.64	100.00	78.57			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.38	100.00	91.89	100.00		100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.58	100.00	90.30			100.00	100.00	u_edn_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_normal_fifo.u_fifo_cnt	100.00	100.00	100.00	100.00		100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Module : prim_fifo_sync

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T30,T95
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T32,T33
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

---

Branch Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	453974554	566440	0	0
DepthKnown_A	454731790	454397828	0	0
RvalidKnown_A	454731790	454397828	0	0
WreadyKnown_A	454731790	454397828	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	454373650	663833	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	453974554	566440	0	0
T3	8850	6075	0	0
T4	690	0	0	0
T8	7150	5466	0	0
T9	0	2975	0	0
T10	0	2210	0	0
T13	232	0	0	0
T14	190	0	0	0
T18	7190	0	0	0
T19	4002	0	0	0
T20	6432	0	0	0
T24	0	657	0	0
T26	0	79	0	0
T45	0	3600	0	0
T50	756	0	0	0
T54	3432	0	0	0
T85	0	9973	0	0
T92	0	12048	0	0
T96	0	2881	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454731790	454397828	0	0
T1	1102	772	0	0
T2	2060	1736	0	0
T3	8850	8748	0	0
T4	1796	1488	0	0
T8	7150	7012	0	0
T13	5612	5248	0	0
T14	3850	3604	0	0
T18	7190	7034	0	0
T19	4002	3808	0	0
T20	6432	6270	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454731790	454397828	0	0
T1	1102	772	0	0
T2	2060	1736	0	0
T3	8850	8748	0	0
T4	1796	1488	0	0
T8	7150	7012	0	0
T13	5612	5248	0	0
T14	3850	3604	0	0
T18	7190	7034	0	0
T19	4002	3808	0	0
T20	6432	6270	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	454731790	454397828	0	0
T1	1102	772	0	0
T2	2060	1736	0	0
T3	8850	8748	0	0
T4	1796	1488	0	0
T8	7150	7012	0	0
T13	5612	5248	0	0
T14	3850	3604	0	0
T18	7190	7034	0	0
T19	4002	3808	0	0
T20	6432	6270	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	454373650	663833	0	0
T1	1102	220	0	0
T2	2060	220	0	0
T3	8850	6075	0	0
T4	1796	0	0	0
T8	7150	5466	0	0
T9	0	2975	0	0
T10	0	2210	0	0
T13	5612	2218	0	0
T14	3850	291	0	0
T18	7190	0	0	0
T19	4002	0	0	0
T20	6432	0	0	0
T24	0	657	0	0
T74	0	353	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T69,T97
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T95
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T31,T32
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_rescmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	226987277	278105	0	0
DepthKnown_A	227365895	227198914	0	0
RvalidKnown_A	227365895	227198914	0	0
WreadyKnown_A	227365895	227198914	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	227186825	326743	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226987277	278105	0	0
T3	4425	2994	0	0
T4	345	0	0	0
T8	3575	2679	0	0
T9	0	1470	0	0
T10	0	1094	0	0
T13	116	0	0	0
T14	95	0	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T24	0	331	0	0
T26	0	33	0	0
T45	0	1769	0	0
T50	378	0	0	0
T54	1716	0	0	0
T85	0	4947	0	0
T92	0	5958	0	0
T96	0	1423	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	227186825	326743	0	0
T1	551	111	0	0
T2	1030	111	0	0
T3	4425	2994	0	0
T4	898	0	0	0
T8	3575	2679	0	0
T9	0	1470	0	0
T10	0	1094	0	0
T13	2806	1110	0	0
T14	1925	147	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T24	0	331	0	0
T74	0	182	0	0

Line Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
TOTAL		14	14	100.00
ALWAYS	69	4	4	100.00
CONT_ASSIGN	81	1	1	100.00
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	100	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
CONT_ASSIGN	120	1	1	100.00
ALWAYS	123	2	2	100.00
CONT_ASSIGN	133	1	1	100.00
CONT_ASSIGN	134	1	1	100.00
CONT_ASSIGN	140	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
69	1	1
70	1	1
71	1	1
72	1	1
			MISSING_ELSE
81	1	1
82	1	1
100	1	1
101	1	1
120	1	1
123	1	1
124	1	1
			MISSING_ELSE
133	1	1
134	1	1
140	1	1

---

Cond Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Covered	Percent
Conditions	14	11	78.57
Logical	14	11	78.57
Non-Logical	0	0
Event	0	0

 LINE       81
 EXPRESSION (((~full_o)) & ((~gen_normal_fifo.under_rst)))
             -----1-----   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       82
 EXPRESSION (((~gen_normal_fifo.empty)) & ((~gen_normal_fifo.under_rst)))
             -------------1------------   ---------------2--------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T1,T2,T3

 LINE       100
 EXPRESSION (wvalid_i & wready_o & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Covered	T29,T30,T98
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       101
 EXPRESSION (rvalid_o & rready_i & ((~gen_normal_fifo.under_rst)))
             ----1---   ----2---   ---------------3--------------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T33,T99
1	0	1	Covered	T1,T2,T3
1	1	0	Not Covered
1	1	1	Covered	T3,T8,T9

---

Branch Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Line No.	Total	Covered	Percent
Branches		5	5	100.00
IF	69	3	3	100.00
IF	123	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	69	if ((!rst_ni))
-2-:	71	if (gen_normal_fifo.under_rst)

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	123	if (gen_normal_fifo.fifo_incr_wptr)

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_edn_core.u_prim_fifo_sync_gencmd

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	226987277	288335	0	0
DepthKnown_A	227365895	227198914	0	0
RvalidKnown_A	227365895	227198914	0	0
WreadyKnown_A	227365895	227198914	0	0
gen_normal_fifo.depthShallNotExceedParamDepth	227186825	337090	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	226987277	288335	0	0
T3	4425	3081	0	0
T4	345	0	0	0
T8	3575	2787	0	0
T9	0	1505	0	0
T10	0	1116	0	0
T13	116	0	0	0
T14	95	0	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T24	0	326	0	0
T26	0	46	0	0
T45	0	1831	0	0
T50	378	0	0	0
T54	1716	0	0	0
T85	0	5026	0	0
T92	0	6090	0	0
T96	0	1458	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	227365895	227198914	0	0
T1	551	386	0	0
T2	1030	868	0	0
T3	4425	4374	0	0
T4	898	744	0	0
T8	3575	3506	0	0
T13	2806	2624	0	0
T14	1925	1802	0	0
T18	3595	3517	0	0
T19	2001	1904	0	0
T20	3216	3135	0	0

gen_normal_fifo.depthShallNotExceedParamDepth

Name	Attempts	Real Successes	Failures	Incomplete
Total	227186825	337090	0	0
T1	551	109	0	0
T2	1030	109	0	0
T3	4425	3081	0	0
T4	898	0	0	0
T8	3575	2787	0	0
T9	0	1505	0	0
T10	0	1116	0	0
T13	2806	1108	0	0
T14	1925	144	0	0
T18	3595	0	0	0
T19	2001	0	0	0
T20	3216	0	0	0
T24	0	326	0	0
T74	0	171	0	0