Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.61	98.24	93.76	97.02	82.08	96.76	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.55	99.92	92.39	82.54	82.08	99.52	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T32,T33,T34

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T16,T17
1	0	Covered	T40,T5,T41

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T22	Yes	T1,T2,T22	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T1,T2,T45	Yes	T1,T2,T45	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T2,T8	Yes	T1,T2,T8	INPUT
edn_i[1].edn_req	Yes	Yes	T8,T23,T18	Yes	T8,T23,T18	INPUT
edn_i[2].edn_req	Yes	Yes	T23,T41,T10	Yes	T23,T41,T10	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T25,T46	Yes	T3,T25,T46	INPUT
edn_i[4].edn_req	Yes	Yes	T25,T30,T47	Yes	T25,T30,T47	INPUT
edn_i[5].edn_req	Yes	Yes	T25,T47,T48	Yes	T25,T47,T48	INPUT
edn_i[6].edn_req	Yes	Yes	T25,T38,T11	Yes	T25,T38,T11	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T2,T8	Yes	T1,T2,T8	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T2,T8	Yes	T1,T2,T8	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T2,T8	Yes	T1,T2,T8	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T23,T18,T33	Yes	T23,T18,T33	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T34,T39,T49	Yes	T8,T18,T34	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T8,T23,T18	Yes	T8,T23,T18	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T23,T10,T50	Yes	T23,T10,T50	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T23,T10,T51	Yes	T23,T10,T51	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T23,T10,T50	Yes	T23,T10,T50	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T25,T46	Yes	T3,T25,T46	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T35,T52,T53	Yes	T25,T21,T35	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T25,T46	Yes	T3,T25,T46	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T25,T47,T54	Yes	T25,T30,T47	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T20,T53,T55	Yes	T47,T19,T20	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T25,T30,T47	Yes	T25,T30,T47	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T48,T49,T56	Yes	T25,T48,T21	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T49,T56,T57	Yes	T48,T21,T49	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T25,T47,T48	Yes	T25,T47,T48	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T25,T11,T58	Yes	T25,T11,T58	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T38,T11,T53	Yes	T25,T38,T11	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T25,T38,T11	Yes	T25,T38,T11	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T8	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T32,T59,T57	Yes	T32,T59,T57	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T22,T60,T61	Yes	T22,T60,T61	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T22,T40,T60	Yes	T22,T40,T60	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T22,T60,T61	Yes	T22,T60,T61	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T22,T40,T60	Yes	T22,T40,T60	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T2,T4	Yes	T1,T2,T4	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	221944712	221774500	0	0
CsrngAppIfOut_A	221944712	221774500	0	0
FpvSecCmCntAlertCheck_A	221944712	104	0	0
FpvSecCmGenCmdFifoRptrCheck_A	221944712	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	221944712	70	0	0
FpvSecCmMainFsmCheck_A	221944712	70	0	0
FpvSecCmRegWeOnehotCheck_A	221944712	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	221944712	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	221944712	70	0	0
IntrEdnCmdReqDoneKnownO_A	221944712	221774500	0	0
TlAReadyKnownO_A	221944712	221774500	0	0
TlDValidKnownO_A	221944712	221774500	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	221944712	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	221944712	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	221944712	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	221944712	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	221944712	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	221944712	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	221944712	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	221944712	526026	0	304
gen_edn_if_asserts[0].EdnDataStable_A	221944712	74011	0	343
gen_edn_if_asserts[0].EdnEndPointOut_A	221944712	221774500	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	221944712	144420	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	221944712	526026	0	304
gen_edn_if_asserts[1].EdnDataStable_A	221944712	52618	0	126
gen_edn_if_asserts[1].EdnEndPointOut_A	221944712	221774500	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	221944712	144420	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	221944712	526026	0	304
gen_edn_if_asserts[2].EdnDataStable_A	221944712	6876	0	96
gen_edn_if_asserts[2].EdnEndPointOut_A	221944712	221774500	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	221944712	144420	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	221944712	526026	0	304
gen_edn_if_asserts[3].EdnDataStable_A	221944712	2083	0	96
gen_edn_if_asserts[3].EdnEndPointOut_A	221944712	221774500	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	221944712	144420	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	221944712	526026	0	304
gen_edn_if_asserts[4].EdnDataStable_A	221944712	52488	0	87
gen_edn_if_asserts[4].EdnEndPointOut_A	221944712	221774500	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	221944712	144420	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	221944712	526026	0	304
gen_edn_if_asserts[5].EdnDataStable_A	221944712	3084	0	72
gen_edn_if_asserts[5].EdnEndPointOut_A	221944712	221774500	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	221944712	144420	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	221944712	526026	0	304
gen_edn_if_asserts[6].EdnDataStable_A	221944712	3806	0	67
gen_edn_if_asserts[6].EdnEndPointOut_A	221944712	221774500	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	221944712	144420	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	104	0	0
T6	881	1	0	0
T7	1852	0	0	0
T13	1314	1	0	0
T14	0	1	0	0
T15	0	20	0	0
T16	0	10	0	0
T34	2705	0	0	0
T35	1089	0	0	0
T39	2078	0	0	0
T54	896	0	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	33024	0	0	0
T68	239746	0	0	0
T69	5017	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	70	0	0
T15	44908	20	0	0
T16	0	10	0	0
T17	0	10	0	0
T62	1908	0	0	0
T70	0	20	0	0
T71	0	10	0	0
T72	219987	0	0	0
T73	1998	0	0	0
T74	162673	0	0	0
T75	1487	0	0	0
T76	2088	0	0	0
T77	1346	0	0	0
T78	1912	0	0	0
T79	23717	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	526026	0	304
T1	681862	1643	0	2
T2	219295	572	0	0
T3	1777	500	0	2
T4	22055	1565	0	2
T8	1247	63	0	0
T9	0	0	0	2
T18	0	0	0	2
T22	836	758	0	2
T23	1106	17	0	0
T24	4201	31	0	0
T25	2235	31	0	0
T26	4716	28	0	0
T45	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	74011	0	343
T1	681862	72	0	0
T2	219295	51	0	1
T3	1777	0	0	0
T4	22055	24	0	0
T8	1247	53	0	1
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	22	0	1
T25	2235	3	0	1
T26	4716	3	0	1
T27	0	0	0	1
T31	0	0	0	1
T32	0	0	0	1
T81	0	3	0	1
T82	0	3	0	0
T83	0	6	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	144420	0	0
T5	2320	1138	0	0
T6	0	364	0	0
T7	0	640	0	0
T13	0	616	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T35	0	7	0	0
T38	0	29	0	0
T39	0	24	0	0
T40	658	215	0	0
T41	0	922	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	327	0	0
T85	1407	0	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	526026	0	304
T1	681862	1643	0	2
T2	219295	572	0	0
T3	1777	500	0	2
T4	22055	1565	0	2
T8	1247	63	0	0
T9	0	0	0	2
T18	0	0	0	2
T22	836	758	0	2
T23	1106	17	0	0
T24	4201	31	0	0
T25	2235	31	0	0
T26	4716	28	0	0
T45	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	52618	0	126
T4	22055	0	0	0
T8	1247	3	0	1
T10	0	3	0	1
T13	0	1	0	0
T18	0	4	0	0
T22	836	0	0	0
T23	1106	5	0	1
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T30	656	0	0	0
T33	0	4	0	0
T34	0	4	0	0
T39	0	1	0	0
T49	0	15	0	1
T50	0	0	0	1
T53	0	0	0	1
T55	0	0	0	1
T57	0	0	0	1
T72	0	0	0	1
T75	0	0	0	1
T81	1574	0	0	0
T82	5320	0	0	0
T86	0	1	0	0

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	144420	0	0
T5	2320	1138	0	0
T6	0	364	0	0
T7	0	640	0	0
T13	0	616	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T35	0	7	0	0
T38	0	29	0	0
T39	0	24	0	0
T40	658	215	0	0
T41	0	922	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	327	0	0
T85	1407	0	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	526026	0	304
T1	681862	1643	0	2
T2	219295	572	0	0
T3	1777	500	0	2
T4	22055	1565	0	2
T8	1247	63	0	0
T9	0	0	0	2
T18	0	0	0	2
T22	836	758	0	2
T23	1106	17	0	0
T24	4201	31	0	0
T25	2235	31	0	0
T26	4716	28	0	0
T45	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	6876	0	96
T4	22055	0	0	0
T10	0	50	0	1
T23	1106	7	0	1
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T30	656	0	0	0
T31	2584	0	0	0
T50	0	3	0	1
T51	0	15	0	1
T53	0	3	0	1
T55	0	63	0	1
T75	0	3	0	1
T76	0	4	0	0
T78	0	4	0	1
T81	1574	0	0	0
T82	5320	0	0	0
T83	14396	0	0	0
T87	0	3	0	1
T88	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	144420	0	0
T5	2320	1138	0	0
T6	0	364	0	0
T7	0	640	0	0
T13	0	616	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T35	0	7	0	0
T38	0	29	0	0
T39	0	24	0	0
T40	658	215	0	0
T41	0	922	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	327	0	0
T85	1407	0	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	526026	0	304
T1	681862	1643	0	2
T2	219295	572	0	0
T3	1777	500	0	2
T4	22055	1565	0	2
T8	1247	63	0	0
T9	0	0	0	2
T18	0	0	0	2
T22	836	758	0	2
T23	1106	17	0	0
T24	4201	31	0	0
T25	2235	31	0	0
T26	4716	28	0	0
T45	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	2083	0	96
T3	1777	4	0	0
T4	22055	0	0	0
T8	1247	0	0	0
T21	0	1	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	3	0	1
T26	4716	0	0	0
T30	656	0	0	0
T35	0	1	0	0
T46	0	4	0	0
T52	0	4	0	0
T53	0	37	0	1
T55	0	0	0	1
T81	1574	0	0	0
T87	0	3	0	1
T88	0	0	0	1
T89	0	3	0	1
T90	0	4	0	1
T91	0	0	0	1
T92	0	0	0	1
T93	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	144420	0	0
T5	2320	1138	0	0
T6	0	364	0	0
T7	0	640	0	0
T13	0	616	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T35	0	7	0	0
T38	0	29	0	0
T39	0	24	0	0
T40	658	215	0	0
T41	0	922	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	327	0	0
T85	1407	0	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	526026	0	304
T1	681862	1643	0	2
T2	219295	572	0	0
T3	1777	500	0	2
T4	22055	1565	0	2
T8	1247	63	0	0
T9	0	0	0	2
T18	0	0	0	2
T22	836	758	0	2
T23	1106	17	0	0
T24	4201	31	0	0
T25	2235	31	0	0
T26	4716	28	0	0
T45	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	52488	0	87
T9	2258	0	0	0
T19	0	4	0	0
T20	0	50	0	1
T25	2235	3	0	1
T26	4716	0	0	0
T27	1346	0	0	0
T30	656	3	0	1
T31	2584	0	0	0
T40	658	0	0	0
T47	0	4	0	0
T49	0	3	0	1
T53	0	55	0	1
T54	0	4	0	0
T55	0	50	0	1
T81	1574	0	0	0
T82	5320	0	0	0
T83	14396	0	0	0
T88	0	0	0	1
T91	0	0	0	1
T94	0	1	0	0
T95	0	0	0	1
T96	0	0	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	144420	0	0
T5	2320	1138	0	0
T6	0	364	0	0
T7	0	640	0	0
T13	0	616	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T35	0	7	0	0
T38	0	29	0	0
T39	0	24	0	0
T40	658	215	0	0
T41	0	922	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	327	0	0
T85	1407	0	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	526026	0	304
T1	681862	1643	0	2
T2	219295	572	0	0
T3	1777	500	0	2
T4	22055	1565	0	2
T8	1247	63	0	0
T9	0	0	0	2
T18	0	0	0	2
T22	836	758	0	2
T23	1106	17	0	0
T24	4201	31	0	0
T25	2235	31	0	0
T26	4716	28	0	0
T45	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	3084	0	72
T9	2258	0	0	0
T21	0	4	0	0
T25	2235	3	0	1
T26	4716	0	0	0
T27	1346	0	0	0
T30	656	0	0	0
T31	2584	0	0	0
T33	0	4	0	1
T40	658	0	0	0
T47	0	1	0	0
T48	0	3	0	1
T49	0	23	0	1
T53	0	3	0	1
T56	0	4	0	0
T57	0	4	0	0
T81	1574	0	0	0
T82	5320	0	0	0
T83	14396	0	0	0
T86	0	4	0	0
T91	0	0	0	1
T96	0	0	0	1
T97	0	0	0	1
T98	0	0	0	1
T99	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	144420	0	0
T5	2320	1138	0	0
T6	0	364	0	0
T7	0	640	0	0
T13	0	616	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T35	0	7	0	0
T38	0	29	0	0
T39	0	24	0	0
T40	658	215	0	0
T41	0	922	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	327	0	0
T85	1407	0	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	526026	0	304
T1	681862	1643	0	2
T2	219295	572	0	0
T3	1777	500	0	2
T4	22055	1565	0	2
T8	1247	63	0	0
T9	0	0	0	2
T18	0	0	0	2
T22	836	758	0	2
T23	1106	17	0	0
T24	4201	31	0	0
T25	2235	31	0	0
T26	4716	28	0	0
T45	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T80	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	3806	0	67
T9	2258	0	0	0
T11	0	23	0	1
T25	2235	3	0	1
T26	4716	0	0	0
T27	1346	0	0	0
T30	656	0	0	0
T31	2584	0	0	0
T38	0	1	0	0
T40	658	0	0	0
T53	0	55	0	1
T55	0	43	0	1
T58	0	3	0	1
T81	1574	0	0	0
T82	5320	0	0	0
T83	14396	0	0	0
T95	0	3	0	1
T100	0	658	0	1
T101	0	3	0	1
T102	0	386	0	1
T103	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	221774500	0	0
T1	681862	681781	0	0
T2	219295	219286	0	0
T3	1777	1686	0	0
T4	22055	21536	0	0
T8	1247	1152	0	0
T22	836	760	0	0
T23	1106	1014	0	0
T24	4201	4137	0	0
T25	2235	2163	0	0
T26	4716	4648	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	221944712	144420	0	0
T5	2320	1138	0	0
T6	0	364	0	0
T7	0	640	0	0
T13	0	616	0	0
T18	2734	0	0	0
T32	2319	0	0	0
T35	0	7	0	0
T38	0	29	0	0
T39	0	24	0	0
T40	658	215	0	0
T41	0	922	0	0
T45	101968	0	0	0
T46	1017	0	0	0
T60	1893	0	0	0
T61	1358	0	0	0
T80	1084	0	0	0
T84	0	327	0	0
T85	1407	0	0	0