Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	222441483	10259214	0	0
boot_gen_cmd_rd_A	222441483	38194	0	0
boot_ins_cmd_rd_A	222441483	43621	0	0
ctrl_rd_A	222441483	37706	0	0
err_code_test_rd_A	222441483	43775	0	0
intr_enable_rd_A	222441483	43255	0	0
max_num_reqs_between_reseeds_rd_A	222441483	38734	0	0
regwen_rd_A	222441483	44455	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222441483	10259214	0	0
T1	681862	25659	0	0
T2	219295	89338	0	0
T3	1777	0	0	0
T4	22055	0	0	0
T8	1247	0	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T45	0	413752	0	0
T68	0	134212	0	0
T74	0	65337	0	0
T164	0	235433	0	0
T195	0	224933	0	0
T196	0	121140	0	0
T197	0	417532	0	0
T198	0	261698	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222441483	38194	0	0
T1	681862	667	0	0
T2	219295	0	0	0
T3	1777	0	0	0
T4	22055	0	0	0
T8	1247	0	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T164	0	6993	0	0
T196	0	3373	0	0
T199	0	3508	0	0
T200	0	4776	0	0
T201	0	7078	0	0
T202	0	3421	0	0
T203	0	1592	0	0
T204	0	6429	0	0
T205	0	7	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222441483	43621	0	0
T1	681862	787	0	0
T2	219295	0	0	0
T3	1777	0	0	0
T4	22055	0	0	0
T8	1247	0	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T164	0	7959	0	0
T196	0	4059	0	0
T199	0	4240	0	0
T200	0	5512	0	0
T201	0	7484	0	0
T202	0	3663	0	0
T203	0	1665	0	0
T204	0	7856	0	0
T205	0	6	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222441483	37706	0	0
T1	681862	877	0	0
T2	219295	0	0	0
T3	1777	0	0	0
T4	22055	0	0	0
T8	1247	0	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T27	0	7	0	0
T28	0	5	0	0
T49	0	2	0	0
T79	0	13	0	0
T141	0	8	0	0
T164	0	6877	0	0
T196	0	3488	0	0
T206	0	2	0	0
T207	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222441483	43775	0	0
T1	681862	873	0	0
T2	219295	0	0	0
T3	1777	0	0	0
T4	22055	0	0	0
T8	1247	0	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T164	0	7805	0	0
T196	0	4137	0	0
T199	0	4018	0	0
T200	0	5445	0	0
T201	0	7672	0	0
T202	0	3868	0	0
T203	0	1856	0	0
T204	0	7733	0	0
T208	0	10	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222441483	43255	0	0
T1	681862	902	0	0
T2	219295	0	0	0
T3	1777	0	0	0
T4	22055	103	0	0
T8	1247	0	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T79	0	28	0	0
T164	0	7008	0	0
T196	0	4163	0	0
T199	0	3706	0	0
T209	0	85	0	0
T210	0	82	0	0
T211	0	5	0	0
T212	0	81	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222441483	38734	0	0
T1	681862	750	0	0
T2	219295	0	0	0
T3	1777	0	0	0
T4	22055	0	0	0
T8	1247	0	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T164	0	6885	0	0
T196	0	3504	0	0
T199	0	3580	0	0
T200	0	5049	0	0
T201	0	6858	0	0
T202	0	3237	0	0
T203	0	1644	0	0
T204	0	6219	0	0
T205	0	10	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	222441483	44455	0	0
T1	681862	911	0	0
T2	219295	0	0	0
T3	1777	0	0	0
T4	22055	0	0	0
T8	1247	0	0	0
T22	836	0	0	0
T23	1106	0	0	0
T24	4201	0	0	0
T25	2235	0	0	0
T26	4716	0	0	0
T164	0	7754	0	0
T196	0	4171	0	0
T199	0	3892	0	0
T200	0	5833	0	0
T201	0	7951	0	0
T202	0	3623	0	0
T203	0	1777	0	0
T204	0	7521	0	0
T205	0	6	0	0