Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.52	98.24	93.82	97.02	81.50	96.76	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.47	99.92	92.48	82.54	81.50	99.52	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T3,T22,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T18,T19,T20
1	0	Covered	T5,T6,T36

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T4,T25	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	INPUT
edn_i[1].edn_req	Yes	Yes	T25,T11,T36	Yes	T25,T11,T36	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T25,T11	Yes	T3,T25,T11	INPUT
edn_i[3].edn_req	Yes	Yes	T25,T11,T24	Yes	T25,T11,T24	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T25,T43	Yes	T3,T25,T43	INPUT
edn_i[5].edn_req	Yes	Yes	T25,T44,T24	Yes	T25,T44,T24	INPUT
edn_i[6].edn_req	Yes	Yes	T25,T21,T6	Yes	T25,T21,T6	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T4,T25	Yes	T1,T4,T25	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T25,T11,T45	Yes	T25,T11,T45	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T36,T45,T46	Yes	T25,T11,T36	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T25,T11,T36	Yes	T25,T11,T36	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T25,T11	Yes	T3,T25,T11	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T3,T11,T45	Yes	T3,T25,T11	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T25,T11	Yes	T3,T25,T11	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T25,T24,T43	Yes	T25,T11,T24	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T45,T47,T48	Yes	T24,T49,T45	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T25,T11,T24	Yes	T25,T11,T24	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T43,T48	Yes	T3,T25,T43	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T43,T50,T51	Yes	T3,T25,T43	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T25,T43	Yes	T3,T25,T43	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T44,T45,T47	Yes	T44,T24,T45	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T45,T47,T50	Yes	T45,T47,T52	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T25,T44,T24	Yes	T25,T44,T24	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T25,T21,T53	Yes	T25,T21,T53	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T25,T21,T53	Yes	T25,T21,T53	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T25,T21,T53	Yes	T25,T21,T53	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T1,T3,T4	Yes	T4,T25,T10	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T1,T4,T25	Yes	T4,T25,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T22,T30,T54	Yes	T22,T30,T54	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T3,T22	Yes	T2,T3,T22	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T2,T5,T6	Yes	T2,T5,T6	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T4,T40,T55	Yes	T4,T40,T55	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T4,T36,T40	Yes	T4,T36,T40	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	168386280	168218887	0	0
CsrngAppIfOut_A	168386280	168218887	0	0
FpvSecCmCntAlertCheck_A	168386280	114	0	0
FpvSecCmGenCmdFifoRptrCheck_A	168386280	70	0	0
FpvSecCmGenCmdFifoWptrCheck_A	168386280	70	0	0
FpvSecCmMainFsmCheck_A	168386280	70	0	0
FpvSecCmRegWeOnehotCheck_A	168386280	70	0	0
FpvSecCmResCmdFifoRptrCheck_A	168386280	70	0	0
FpvSecCmResCmdFifoWptrCheck_A	168386280	70	0	0
IntrEdnCmdReqDoneKnownO_A	168386280	168218887	0	0
TlAReadyKnownO_A	168386280	168218887	0	0
TlDValidKnownO_A	168386280	168218887	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	168386280	70	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	168386280	70	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	168386280	70	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	168386280	70	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	168386280	70	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	168386280	70	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	168386280	70	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	168386280	506662	0	300
gen_edn_if_asserts[0].EdnDataStable_A	168386280	21065	0	366
gen_edn_if_asserts[0].EdnEndPointOut_A	168386280	168218887	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	168386280	147829	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	168386280	506662	0	300
gen_edn_if_asserts[1].EdnDataStable_A	168386280	3901	0	116
gen_edn_if_asserts[1].EdnEndPointOut_A	168386280	168218887	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	168386280	147829	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	168386280	506662	0	300
gen_edn_if_asserts[2].EdnDataStable_A	168386280	6021	0	116
gen_edn_if_asserts[2].EdnEndPointOut_A	168386280	168218887	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	168386280	147829	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	168386280	506662	0	300
gen_edn_if_asserts[3].EdnDataStable_A	168386280	7026	0	100
gen_edn_if_asserts[3].EdnEndPointOut_A	168386280	168218887	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	168386280	147829	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	168386280	506662	0	300
gen_edn_if_asserts[4].EdnDataStable_A	168386280	2175	0	84
gen_edn_if_asserts[4].EdnEndPointOut_A	168386280	168218887	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	168386280	147829	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	168386280	506662	0	300
gen_edn_if_asserts[5].EdnDataStable_A	168386280	3658	0	82
gen_edn_if_asserts[5].EdnEndPointOut_A	168386280	168218887	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	168386280	147829	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	168386280	506662	0	300
gen_edn_if_asserts[6].EdnDataStable_A	168386280	3526	0	72
gen_edn_if_asserts[6].EdnEndPointOut_A	168386280	168218887	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	168386280	147829	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	114	0	0
T6	1063	1	0	0
T16	0	1	0	0
T17	0	1	0	0
T18	0	10	0	0
T22	2445	0	0	0
T36	851	0	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T56	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	70	0	0
T18	24972	10	0	0
T19	0	10	0	0
T20	0	20	0	0
T65	0	20	0	0
T66	0	10	0	0
T67	1101	0	0	0
T68	1907	0	0	0
T69	2377	0	0	0
T70	1084	0	0	0
T71	1417	0	0	0
T72	3972	0	0	0
T73	731	0	0	0
T74	1815	0	0	0
T75	1098	0	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	506662	0	300
T1	2278	94	0	0
T2	1063	962	0	2
T3	1918	243	0	0
T4	15983	2787	0	0
T10	6594	165	0	0
T11	2921	55	0	0
T12	2421	212	0	0
T21	3575	323	0	0
T24	0	0	0	2
T25	2792	47	0	0
T26	1051	88	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T44	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	21065	0	366
T1	2278	11	0	1
T2	1063	0	0	0
T3	1918	0	0	0
T4	15983	19	0	1
T10	6594	1131	0	1
T11	2921	3	0	1
T12	2421	67	0	1
T21	3575	0	0	0
T25	2792	42	0	1
T26	1051	3	0	1
T62	0	12	0	1
T63	0	3	0	1
T64	0	64	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	147829	0	0
T5	1620	952	0	0
T6	1063	614	0	0
T16	0	640	0	0
T17	0	354	0	0
T33	0	25	0	0
T36	851	295	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1116	0	0
T81	0	252	0	0
T82	0	942	0	0
T83	0	622	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	506662	0	300
T1	2278	94	0	0
T2	1063	962	0	2
T3	1918	243	0	0
T4	15983	2787	0	0
T10	6594	165	0	0
T11	2921	55	0	0
T12	2421	212	0	0
T21	3575	323	0	0
T24	0	0	0	2
T25	2792	47	0	0
T26	1051	88	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T44	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	3901	0	116
T5	1620	0	0	0
T6	1063	0	0	0
T10	6594	0	0	0
T11	2921	19	0	1
T12	2421	0	0	0
T21	3575	0	0	0
T25	2792	3	0	1
T26	1051	0	0	0
T36	851	1	0	0
T45	0	22	0	1
T46	0	55	0	1
T48	0	3	0	1
T51	0	0	0	1
T62	5584	0	0	0
T84	0	3	0	1
T85	0	23	0	1
T86	0	4	0	0
T87	0	4	0	0
T88	0	0	0	1
T89	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	147829	0	0
T5	1620	952	0	0
T6	1063	614	0	0
T16	0	640	0	0
T17	0	354	0	0
T33	0	25	0	0
T36	851	295	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1116	0	0
T81	0	252	0	0
T82	0	942	0	0
T83	0	622	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	506662	0	300
T1	2278	94	0	0
T2	1063	962	0	2
T3	1918	243	0	0
T4	15983	2787	0	0
T10	6594	165	0	0
T11	2921	55	0	0
T12	2421	212	0	0
T21	3575	323	0	0
T24	0	0	0	2
T25	2792	47	0	0
T26	1051	88	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T44	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	6021	0	116
T3	1918	4	0	0
T4	15983	0	0	0
T5	1620	0	0	0
T6	1063	0	0	0
T10	6594	0	0	0
T11	2921	279	0	1
T12	2421	0	0	0
T21	3575	3	0	1
T25	2792	3	0	1
T26	1051	0	0	0
T43	0	3	0	1
T45	0	43	0	1
T46	0	55	0	1
T47	0	3	0	1
T48	0	527	0	1
T52	0	44	0	1
T84	0	0	0	1

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	147829	0	0
T5	1620	952	0	0
T6	1063	614	0	0
T16	0	640	0	0
T17	0	354	0	0
T33	0	25	0	0
T36	851	295	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1116	0	0
T81	0	252	0	0
T82	0	942	0	0
T83	0	622	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	506662	0	300
T1	2278	94	0	0
T2	1063	962	0	2
T3	1918	243	0	0
T4	15983	2787	0	0
T10	6594	165	0	0
T11	2921	55	0	0
T12	2421	212	0	0
T21	3575	323	0	0
T24	0	0	0	2
T25	2792	47	0	0
T26	1051	88	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T44	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	7026	0	100
T5	1620	0	0	0
T6	1063	0	0	0
T10	6594	0	0	0
T11	2921	3	0	1
T12	2421	0	0	0
T21	3575	0	0	0
T24	0	4	0	0
T25	2792	3	0	1
T26	1051	0	0	0
T36	851	0	0	0
T43	0	3	0	1
T45	0	53	0	1
T46	0	3	0	1
T47	0	700	0	1
T48	0	23	0	1
T49	0	3	0	1
T52	0	3	0	1
T62	5584	0	0	0
T84	0	0	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	147829	0	0
T5	1620	952	0	0
T6	1063	614	0	0
T16	0	640	0	0
T17	0	354	0	0
T33	0	25	0	0
T36	851	295	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1116	0	0
T81	0	252	0	0
T82	0	942	0	0
T83	0	622	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	506662	0	300
T1	2278	94	0	0
T2	1063	962	0	2
T3	1918	243	0	0
T4	15983	2787	0	0
T10	6594	165	0	0
T11	2921	55	0	0
T12	2421	212	0	0
T21	3575	323	0	0
T24	0	0	0	2
T25	2792	47	0	0
T26	1051	88	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T44	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	2175	0	84
T3	1918	4	0	1
T4	15983	0	0	0
T5	1620	0	0	0
T6	1063	0	0	0
T10	6594	0	0	0
T11	2921	0	0	0
T12	2421	0	0	0
T21	3575	0	0	0
T25	2792	3	0	1
T26	1051	0	0	0
T43	0	53	0	1
T48	0	3	0	1
T50	0	56	0	1
T51	0	37	0	1
T90	0	3	0	1
T91	0	15	0	1
T92	0	3	0	1
T93	0	3	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	147829	0	0
T5	1620	952	0	0
T6	1063	614	0	0
T16	0	640	0	0
T17	0	354	0	0
T33	0	25	0	0
T36	851	295	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1116	0	0
T81	0	252	0	0
T82	0	942	0	0
T83	0	622	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	506662	0	300
T1	2278	94	0	0
T2	1063	962	0	2
T3	1918	243	0	0
T4	15983	2787	0	0
T10	6594	165	0	0
T11	2921	55	0	0
T12	2421	212	0	0
T21	3575	323	0	0
T24	0	0	0	2
T25	2792	47	0	0
T26	1051	88	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T44	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	3658	0	82
T5	1620	0	0	0
T6	1063	0	0	0
T10	6594	0	0	0
T11	2921	0	0	0
T12	2421	0	0	0
T21	3575	0	0	0
T24	0	1	0	0
T25	2792	3	0	1
T26	1051	0	0	0
T36	851	0	0	0
T44	0	4	0	0
T45	0	52	0	1
T46	0	3	0	1
T47	0	12	0	1
T48	0	3	0	1
T50	0	63	0	1
T52	0	3	0	1
T62	5584	0	0	0
T94	0	3	0	1
T95	0	0	0	1
T96	0	0	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	147829	0	0
T5	1620	952	0	0
T6	1063	614	0	0
T16	0	640	0	0
T17	0	354	0	0
T33	0	25	0	0
T36	851	295	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1116	0	0
T81	0	252	0	0
T82	0	942	0	0
T83	0	622	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	506662	0	300
T1	2278	94	0	0
T2	1063	962	0	2
T3	1918	243	0	0
T4	15983	2787	0	0
T10	6594	165	0	0
T11	2921	55	0	0
T12	2421	212	0	0
T21	3575	323	0	0
T24	0	0	0	2
T25	2792	47	0	0
T26	1051	88	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T44	0	0	0	2
T76	0	0	0	2
T77	0	0	0	2
T78	0	0	0	2
T79	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	3526	0	72
T5	1620	0	0	0
T6	1063	0	0	0
T10	6594	0	0	0
T11	2921	0	0	0
T12	2421	0	0	0
T21	3575	179	0	1
T25	2792	24	0	1
T26	1051	0	0	0
T34	0	1	0	0
T36	851	0	0	0
T46	0	30	0	1
T48	0	24	0	1
T50	0	3	0	1
T53	0	627	0	1
T62	5584	0	0	0
T84	0	3	0	1
T91	0	3	0	1
T97	0	3	0	1
T98	0	0	0	1

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	168218887	0	0
T1	2278	2201	0	0
T2	1063	964	0	0
T3	1918	1856	0	0
T4	15983	15499	0	0
T10	6594	6497	0	0
T11	2921	2838	0	0
T12	2421	2371	0	0
T21	3575	3489	0	0
T25	2792	2704	0	0
T26	1051	973	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168386280	147829	0	0
T5	1620	952	0	0
T6	1063	614	0	0
T16	0	640	0	0
T17	0	354	0	0
T33	0	25	0	0
T36	851	295	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T62	5584	0	0	0
T63	1356	0	0	0
T64	2273	0	0	0
T80	0	1116	0	0
T81	0	252	0	0
T82	0	942	0	0
T83	0	622	0	0