Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	168898010	7638058	0	0
boot_gen_cmd_rd_A	168898010	44286	0	0
boot_ins_cmd_rd_A	168898010	50435	0	0
ctrl_rd_A	168898010	44148	0	0
err_code_test_rd_A	168898010	50539	0	0
intr_enable_rd_A	168898010	49758	0	0
max_num_reqs_between_reseeds_rd_A	168898010	45785	0	0
regwen_rd_A	168898010	51181	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168898010	7638058	0	0
T22	2445	0	0	0
T23	1430	0	0	0
T24	3794	0	0	0
T33	2126	0	0	0
T40	146205	59003	0	0
T41	0	113624	0	0
T42	0	213260	0	0
T43	5277	0	0	0
T49	874	0	0	0
T55	8485	0	0	0
T76	1043	0	0	0
T97	1404	0	0	0
T162	0	28840	0	0
T196	0	194294	0	0
T197	0	137736	0	0
T198	0	48077	0	0
T199	0	42250	0	0
T200	0	442326	0	0
T201	0	83795	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168898010	44286	0	0
T7	675	0	0	0
T34	597	0	0	0
T35	797	0	0	0
T51	4708	0	0	0
T54	2502	0	0	0
T89	1570	0	0	0
T162	875396	841	0	0
T163	21198	0	0	0
T202	0	2608	0	0
T203	0	2589	0	0
T204	0	4953	0	0
T205	0	5541	0	0
T206	0	4860	0	0
T207	0	2315	0	0
T208	0	890	0	0
T209	0	4716	0	0
T210	0	4494	0	0
T211	687	0	0	0
T212	1452	0	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168898010	50435	0	0
T7	675	0	0	0
T34	597	0	0	0
T35	797	0	0	0
T51	4708	0	0	0
T54	2502	0	0	0
T89	1570	0	0	0
T162	875396	1037	0	0
T163	21198	0	0	0
T202	0	2746	0	0
T203	0	3135	0	0
T204	0	5641	0	0
T205	0	6365	0	0
T206	0	5452	0	0
T207	0	2904	0	0
T208	0	1125	0	0
T209	0	5404	0	0
T210	0	4765	0	0
T211	687	0	0	0
T212	1452	0	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168898010	44148	0	0
T22	2445	7	0	0
T23	1430	0	0	0
T24	3794	0	0	0
T36	851	1	0	0
T40	146205	0	0	0
T44	3051	0	0	0
T53	5251	0	0	0
T55	8485	0	0	0
T63	1356	0	0	0
T64	2273	6	0	0
T159	0	4	0	0
T161	0	6	0	0
T162	0	970	0	0
T213	0	8	0	0
T214	0	1	0	0
T215	0	6	0	0
T216	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168898010	50539	0	0
T7	675	0	0	0
T34	597	0	0	0
T35	797	0	0	0
T51	4708	0	0	0
T54	2502	0	0	0
T89	1570	0	0	0
T162	875396	1009	0	0
T163	21198	0	0	0
T202	0	2914	0	0
T203	0	2800	0	0
T204	0	5923	0	0
T205	0	6220	0	0
T206	0	5084	0	0
T207	0	2875	0	0
T208	0	1071	0	0
T209	0	5571	0	0
T210	0	4707	0	0
T211	687	0	0	0
T212	1452	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168898010	49758	0	0
T45	3845	0	0	0
T47	5584	0	0	0
T48	5022	0	0	0
T77	1185	0	0	0
T78	850	0	0	0
T80	2466	0	0	0
T160	21230	13	0	0
T161	0	55	0	0
T162	0	962	0	0
T163	0	9	0	0
T164	28583	0	0	0
T166	1330	0	0	0
T202	0	2835	0	0
T203	0	2932	0	0
T204	0	5239	0	0
T205	0	5910	0	0
T217	0	17	0	0
T218	0	95	0	0
T219	1729	0	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168898010	45785	0	0
T7	675	0	0	0
T34	597	0	0	0
T35	797	0	0	0
T51	4708	0	0	0
T54	2502	0	0	0
T89	1570	0	0	0
T162	875396	837	0	0
T163	21198	0	0	0
T202	0	2465	0	0
T203	0	2621	0	0
T204	0	5266	0	0
T205	0	5420	0	0
T206	0	4656	0	0
T207	0	2515	0	0
T208	0	926	0	0
T209	0	4888	0	0
T210	0	4465	0	0
T211	687	0	0	0
T212	1452	0	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	168898010	51181	0	0
T7	675	0	0	0
T34	597	0	0	0
T35	797	0	0	0
T51	4708	0	0	0
T54	2502	0	0	0
T89	1570	0	0	0
T162	875396	995	0	0
T163	21198	0	0	0
T202	0	2937	0	0
T203	0	3017	0	0
T204	0	5752	0	0
T205	0	6452	0	0
T206	0	5501	0	0
T207	0	2557	0	0
T208	0	1068	0	0
T209	0	5137	0	0
T210	0	4685	0	0
T211	687	0	0	0
T212	1452	0	0	0