Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	94.44		83.33	100.00			100.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.44		83.33	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.62	98.24	93.82	97.02	82.08	96.76	99.77

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
edn_csr_assert	100.00						100.00
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
gen_alert_tx[1].u_prim_alert_sender	100.00			100.00
tlul_assert_device	100.00	100.00				100.00	100.00
u_edn_core	92.57	99.92	92.48	82.54	82.08	99.52	98.88
u_edn_cov_if	25.00	50.00	0.00
u_reg	96.95	95.02	97.57	100.00		92.16	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Cond Coverage for Module : edn

	Total	Covered	Percent
Conditions	6	5	83.33
Logical	6	5	83.33
Non-Logical	0	0
Event	0	0

 LINE       98
 EXPRESSION (alert[0] || intg_err_alert[0])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T26,T29,T30

 LINE       98
 EXPRESSION (alert[1] || intg_err_alert[1])
             ----1---    --------2--------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T15,T18,T19
1	0	Covered	T1,T15,T35

---

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	69	69	100.00
Total Bits	1172	1172	100.00
Total Bits 0->1	586	586	100.00
Total Bits 1->0	586	586	100.00

Ports	69	69	100.00
Port Bits	1172	1172	100.00
Port Bits 0->1	586	586	100.00
Port Bits 1->0	586	586	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T4	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T2,T10,T26	Yes	T2,T10,T26	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T40,T41,T42	Yes	T40,T41,T42	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T3,*T4	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
edn_i[0].edn_req	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
edn_i[1].edn_req	Yes	Yes	T3,T9,T43	Yes	T3,T9,T43	INPUT
edn_i[2].edn_req	Yes	Yes	T3,T9,T44	Yes	T3,T9,T44	INPUT
edn_i[3].edn_req	Yes	Yes	T3,T9,T26	Yes	T3,T9,T26	INPUT
edn_i[4].edn_req	Yes	Yes	T3,T10,T44	Yes	T3,T10,T44	INPUT
edn_i[5].edn_req	Yes	Yes	T9,T20,T27	Yes	T9,T20,T27	INPUT
edn_i[6].edn_req	Yes	Yes	T3,T9,T44	Yes	T3,T9,T44	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T1,T4,T9	Yes	T1,T3,T4	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T1,T4,T9	Yes	T1,T4,T9	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T3,T9,T43	Yes	T3,T9,T43	OUTPUT
edn_o[1].edn_fips	Yes	Yes	T9,T43,T28	Yes	T9,T43,T28	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T3,T9,T43	Yes	T3,T9,T43	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T3,T9,T44	Yes	T3,T9,T44	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T9,T21,T45	Yes	T9,T44,T21	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T3,T9,T44	Yes	T3,T9,T44	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T3,T9,T26	Yes	T3,T9,T26	OUTPUT
edn_o[3].edn_fips	Yes	Yes	T9,T12,T43	Yes	T3,T9,T12	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T3,T9,T26	Yes	T3,T9,T26	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T3,T10,T44	Yes	T3,T10,T44	OUTPUT
edn_o[4].edn_fips	Yes	Yes	T44,T43,T46	Yes	T3,T10,T44	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T3,T10,T44	Yes	T3,T10,T44	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T9,T20,T27	Yes	T9,T20,T27	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T12,T43,T47	Yes	T20,T27,T44	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T9,T20,T27	Yes	T9,T20,T27	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T3,T9,T44	Yes	T3,T9,T44	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T44,T43,T48	Yes	T9,T44,T43	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T3,T9,T44	Yes	T3,T9,T44	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T3,T9,T5	Yes	T3,T4,T9	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T3,T9,T10	Yes	T3,T9,T10	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
csrng_cmd_i.csrng_rsp_sts[2:0]	Yes	Yes	T29,T30,T49	Yes	T29,T30,T49	INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T1,T3,T4	Yes	T1,T3,T4	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T2,T26,T50	Yes	T2,T26,T50	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T1,T2,T50	Yes	T1,T2,T50	INPUT
alert_rx_i[1].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[1].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T2,T26,T50	Yes	T2,T26,T50	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T1,T2,T50	Yes	T1,T2,T50	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T5,T51,T40	Yes	T5,T51,T40	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T1,T4,T5	Yes	T1,T4,T5	OUTPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : edn

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	47	47	100.00	47	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	47	47	100.00	47	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertTxKnownO_A	216388375	216232523	0	0
CsrngAppIfOut_A	216388375	216232523	0	0
FpvSecCmCntAlertCheck_A	216388375	105	0	0
FpvSecCmGenCmdFifoRptrCheck_A	216388375	60	0	0
FpvSecCmGenCmdFifoWptrCheck_A	216388375	60	0	0
FpvSecCmMainFsmCheck_A	216388375	60	0	0
FpvSecCmRegWeOnehotCheck_A	216388375	60	0	0
FpvSecCmResCmdFifoRptrCheck_A	216388375	60	0	0
FpvSecCmResCmdFifoWptrCheck_A	216388375	60	0	0
IntrEdnCmdReqDoneKnownO_A	216388375	216232523	0	0
TlAReadyKnownO_A	216388375	216232523	0	0
TlDValidKnownO_A	216388375	216232523	0	0
gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A	216388375	60	0	0
gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A	216388375	60	0	0
gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A	216388375	60	0	0
gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A	216388375	60	0	0
gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A	216388375	60	0	0
gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A	216388375	60	0	0
gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A	216388375	60	0	0
gen_edn_if_asserts[0].EdnDataStableDisable_A	216388375	519861	0	310
gen_edn_if_asserts[0].EdnDataStable_A	216388375	20842	0	335
gen_edn_if_asserts[0].EdnEndPointOut_A	216388375	216232523	0	0
gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A	216388375	140541	0	0
gen_edn_if_asserts[1].EdnDataStableDisable_A	216388375	519861	0	310
gen_edn_if_asserts[1].EdnDataStable_A	216388375	2768	0	131
gen_edn_if_asserts[1].EdnEndPointOut_A	216388375	216232523	0	0
gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A	216388375	140541	0	0
gen_edn_if_asserts[2].EdnDataStableDisable_A	216388375	519861	0	310
gen_edn_if_asserts[2].EdnDataStable_A	216388375	7727	0	132
gen_edn_if_asserts[2].EdnEndPointOut_A	216388375	216232523	0	0
gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A	216388375	140541	0	0
gen_edn_if_asserts[3].EdnDataStableDisable_A	216388375	519861	0	310
gen_edn_if_asserts[3].EdnDataStable_A	216388375	5365	0	109
gen_edn_if_asserts[3].EdnEndPointOut_A	216388375	216232523	0	0
gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A	216388375	140541	0	0
gen_edn_if_asserts[4].EdnDataStableDisable_A	216388375	519861	0	310
gen_edn_if_asserts[4].EdnDataStable_A	216388375	4188	0	92
gen_edn_if_asserts[4].EdnEndPointOut_A	216388375	216232523	0	0
gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A	216388375	140541	0	0
gen_edn_if_asserts[5].EdnDataStableDisable_A	216388375	519861	0	310
gen_edn_if_asserts[5].EdnDataStable_A	216388375	3327	0	93
gen_edn_if_asserts[5].EdnEndPointOut_A	216388375	216232523	0	0
gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A	216388375	140541	0	0
gen_edn_if_asserts[6].EdnDataStableDisable_A	216388375	519861	0	310
gen_edn_if_asserts[6].EdnDataStable_A	216388375	4283	0	88
gen_edn_if_asserts[6].EdnEndPointOut_A	216388375	216232523	0	0
gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A	216388375	140541	0	0

AlertTxKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

CsrngAppIfOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

FpvSecCmCntAlertCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	105	0	0
T8	0	1	0	0
T15	24403	10	0	0
T16	1414	1	0	0
T17	0	1	0	0
T18	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T57	1142	0	0	0

FpvSecCmGenCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

FpvSecCmGenCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

FpvSecCmMainFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

FpvSecCmResCmdFifoRptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

FpvSecCmResCmdFifoWptrCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

IntrEdnCmdReqDoneKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

gen_edn_fsm_asserts[0].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

gen_edn_fsm_asserts[1].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

gen_edn_fsm_asserts[2].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

gen_edn_fsm_asserts[3].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

gen_edn_fsm_asserts[4].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

gen_edn_fsm_asserts[5].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

gen_edn_fsm_asserts[6].FpvSecCmAckFsmCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	60	0	0
T15	24403	10	0	0
T16	1414	0	0	0
T18	0	10	0	0
T19	0	10	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T58	0	10	0	0
T59	0	20	0	0

gen_edn_if_asserts[0].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	519861	0	310
T1	746	226	0	0
T2	1510	1441	0	2
T3	1539	12	0	0
T4	10267	90	0	0
T5	15243	5103	0	0
T9	8338	397	0	0
T10	2018	1144	0	2
T11	5944	67	0	0
T15	0	0	0	2
T20	3784	409	0	0
T22	1786	12	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T50	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[0].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	20842	0	335
T1	746	1	0	0
T2	1510	0	0	0
T3	1539	3	0	1
T4	10267	10	0	1
T5	15243	22	0	1
T9	8338	39	0	1
T10	2018	0	0	0
T11	5944	795	0	1
T20	3784	0	0	0
T21	0	0	0	1
T22	1786	3	0	1
T44	0	3	0	1
T51	0	33	0	1
T63	0	14	0	1

gen_edn_if_asserts[0].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

gen_edn_if_asserts[0].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	140541	0	0
T1	746	300	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	396	0	0
T7	0	1148	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7484	0	0
T16	0	854	0	0
T17	0	464	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T31	0	7	0	0
T35	0	1115	0	0
T64	0	332	0	0
T65	0	860	0	0

gen_edn_if_asserts[1].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	519861	0	310
T1	746	226	0	0
T2	1510	1441	0	2
T3	1539	12	0	0
T4	10267	90	0	0
T5	15243	5103	0	0
T9	8338	397	0	0
T10	2018	1144	0	2
T11	5944	67	0	0
T15	0	0	0	2
T20	3784	409	0	0
T22	1786	12	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T50	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[1].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	2768	0	131
T3	1539	3	0	1
T4	10267	0	0	0
T5	15243	0	0	0
T7	0	1	0	0
T9	8338	20	0	1
T10	2018	0	0	0
T11	5944	0	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T26	1934	0	0	0
T28	0	4	0	0
T29	0	4	0	1
T31	0	1	0	0
T43	0	54	0	1
T45	0	3	0	1
T46	0	0	0	1
T48	0	42	0	1
T50	962	0	0	0
T66	0	3	0	1
T67	0	0	0	1
T68	0	0	0	1

gen_edn_if_asserts[1].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

gen_edn_if_asserts[1].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	140541	0	0
T1	746	300	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	396	0	0
T7	0	1148	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7484	0	0
T16	0	854	0	0
T17	0	464	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T31	0	7	0	0
T35	0	1115	0	0
T64	0	332	0	0
T65	0	860	0	0

gen_edn_if_asserts[2].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	519861	0	310
T1	746	226	0	0
T2	1510	1441	0	2
T3	1539	12	0	0
T4	10267	90	0	0
T5	15243	5103	0	0
T9	8338	397	0	0
T10	2018	1144	0	2
T11	5944	67	0	0
T15	0	0	0	2
T20	3784	409	0	0
T22	1786	12	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T50	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[2].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	7727	0	132
T3	1539	3	0	1
T4	10267	0	0	0
T5	15243	0	0	0
T9	8338	44	0	1
T10	2018	0	0	0
T11	5944	0	0	0
T20	3784	0	0	0
T21	0	15	0	1
T22	1786	0	0	0
T26	1934	0	0	0
T43	0	3	0	1
T44	0	3	0	1
T45	0	530	0	1
T46	0	0	0	1
T50	962	0	0	0
T67	0	54	0	1
T69	0	3	0	1
T70	0	3	0	1
T71	0	1	0	0

gen_edn_if_asserts[2].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

gen_edn_if_asserts[2].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	140541	0	0
T1	746	300	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	396	0	0
T7	0	1148	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7484	0	0
T16	0	854	0	0
T17	0	464	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T31	0	7	0	0
T35	0	1115	0	0
T64	0	332	0	0
T65	0	860	0	0

gen_edn_if_asserts[3].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	519861	0	310
T1	746	226	0	0
T2	1510	1441	0	2
T3	1539	12	0	0
T4	10267	90	0	0
T5	15243	5103	0	0
T9	8338	397	0	0
T10	2018	1144	0	2
T11	5944	67	0	0
T15	0	0	0	2
T20	3784	409	0	0
T22	1786	12	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T50	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[3].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	5365	0	109
T3	1539	3	0	1
T4	10267	0	0	0
T5	15243	0	0	0
T9	8338	836	0	1
T10	2018	0	0	0
T11	5944	0	0	0
T12	0	17	0	1
T20	3784	0	0	0
T21	0	3	0	1
T22	1786	0	0	0
T26	1934	4	0	1
T43	0	38	0	1
T44	0	3	0	1
T45	0	3	0	1
T50	962	0	0	0
T66	0	3	0	1
T72	0	35	0	1

gen_edn_if_asserts[3].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

gen_edn_if_asserts[3].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	140541	0	0
T1	746	300	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	396	0	0
T7	0	1148	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7484	0	0
T16	0	854	0	0
T17	0	464	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T31	0	7	0	0
T35	0	1115	0	0
T64	0	332	0	0
T65	0	860	0	0

gen_edn_if_asserts[4].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	519861	0	310
T1	746	226	0	0
T2	1510	1441	0	2
T3	1539	12	0	0
T4	10267	90	0	0
T5	15243	5103	0	0
T9	8338	397	0	0
T10	2018	1144	0	2
T11	5944	67	0	0
T15	0	0	0	2
T20	3784	409	0	0
T22	1786	12	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T50	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[4].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	4188	0	92
T3	1539	3	0	1
T4	10267	0	0	0
T5	15243	0	0	0
T9	8338	0	0	0
T10	2018	4	0	0
T11	5944	0	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T26	1934	0	0	0
T30	0	4	0	1
T43	0	1141	0	1
T44	0	42	0	1
T46	0	40	0	1
T47	0	0	0	1
T48	0	3	0	1
T50	962	0	0	0
T66	0	3	0	1
T73	0	3	0	1
T74	0	4	0	1

gen_edn_if_asserts[4].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

gen_edn_if_asserts[4].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	140541	0	0
T1	746	300	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	396	0	0
T7	0	1148	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7484	0	0
T16	0	854	0	0
T17	0	464	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T31	0	7	0	0
T35	0	1115	0	0
T64	0	332	0	0
T65	0	860	0	0

gen_edn_if_asserts[5].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	519861	0	310
T1	746	226	0	0
T2	1510	1441	0	2
T3	1539	12	0	0
T4	10267	90	0	0
T5	15243	5103	0	0
T9	8338	397	0	0
T10	2018	1144	0	2
T11	5944	67	0	0
T15	0	0	0	2
T20	3784	409	0	0
T22	1786	12	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T50	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[5].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	3327	0	93
T5	15243	0	0	0
T9	8338	3	0	1
T10	2018	0	0	0
T11	5944	0	0	0
T12	0	23	0	1
T20	3784	15	0	1
T22	1786	0	0	0
T26	1934	0	0	0
T27	976	3	0	1
T43	0	60	0	1
T44	0	3	0	1
T46	0	3	0	1
T47	0	52	0	1
T48	0	3	0	1
T50	962	0	0	0
T51	29252	0	0	0
T73	0	3	0	1

gen_edn_if_asserts[5].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

gen_edn_if_asserts[5].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	140541	0	0
T1	746	300	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	396	0	0
T7	0	1148	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7484	0	0
T16	0	854	0	0
T17	0	464	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T31	0	7	0	0
T35	0	1115	0	0
T64	0	332	0	0
T65	0	860	0	0

gen_edn_if_asserts[6].EdnDataStableDisable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	519861	0	310
T1	746	226	0	0
T2	1510	1441	0	2
T3	1539	12	0	0
T4	10267	90	0	0
T5	15243	5103	0	0
T9	8338	397	0	0
T10	2018	1144	0	2
T11	5944	67	0	0
T15	0	0	0	2
T20	3784	409	0	0
T22	1786	12	0	0
T40	0	0	0	2
T41	0	0	0	2
T42	0	0	0	2
T50	0	0	0	2
T60	0	0	0	2
T61	0	0	0	2
T62	0	0	0	2

gen_edn_if_asserts[6].EdnDataStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	4283	0	88
T3	1539	3	0	1
T4	10267	0	0	0
T5	15243	0	0	0
T9	8338	9	0	1
T10	2018	0	0	0
T11	5944	0	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T26	1934	0	0	0
T43	0	46	0	1
T44	0	37	0	1
T45	0	3	0	1
T46	0	3	0	1
T47	0	0	0	1
T48	0	37	0	1
T50	962	0	0	0
T69	0	38	0	1
T73	0	50	0	1
T74	0	4	0	0

gen_edn_if_asserts[6].EdnEndPointOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	216232523	0	0
T1	746	574	0	0
T2	1510	1443	0	0
T3	1539	1445	0	0
T4	10267	10041	0	0
T5	15243	14396	0	0
T9	8338	8242	0	0
T10	2018	1966	0	0
T11	5944	5893	0	0
T20	3784	3698	0	0
T22	1786	1713	0	0

gen_edn_if_asserts[6].EdnFatalAlertNoRsp_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216388375	140541	0	0
T1	746	300	0	0
T2	1510	0	0	0
T3	1539	0	0	0
T4	10267	0	0	0
T5	15243	0	0	0
T6	0	396	0	0
T7	0	1148	0	0
T9	8338	0	0	0
T10	2018	0	0	0
T11	5944	0	0	0
T15	0	7484	0	0
T16	0	854	0	0
T17	0	464	0	0
T20	3784	0	0	0
T22	1786	0	0	0
T31	0	7	0	0
T35	0	1115	0	0
T64	0	332	0	0
T65	0	860	0	0