Unified Coverage Report :: Module :: edn_csr_assert_fpv

Module : edn_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_edn_csr_assert_0/edn_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.edn_csr_assert	100.00						100.00

---

Module Instance : tb.dut.edn_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.44		83.33	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : edn_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	216865151	9891681	0	0
boot_gen_cmd_rd_A	216865151	64739	0	0
boot_ins_cmd_rd_A	216865151	73720	0	0
ctrl_rd_A	216865151	65028	0	0
err_code_test_rd_A	216865151	75192	0	0
intr_enable_rd_A	216865151	71952	0	0
max_num_reqs_between_reseeds_rd_A	216865151	65528	0	0
regwen_rd_A	216865151	74550	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216865151	9891681	0	0
T15	24403	0	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T40	522167	182637	0	0
T41	126339	69558	0	0
T42	245448	136898	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T62	0	337915	0	0
T142	0	523654	0	0
T143	0	461106	0	0
T181	0	57356	0	0
T182	0	279035	0	0
T183	0	190238	0	0
T184	0	106699	0	0

boot_gen_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216865151	64739	0	0
T15	24403	0	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T40	522167	5616	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T143	0	7277	0	0
T182	0	4176	0	0
T185	0	2114	0	0
T186	0	1635	0	0
T187	0	4610	0	0
T188	0	1214	0	0
T189	0	6279	0	0
T190	0	3558	0	0
T191	0	2611	0	0

boot_ins_cmd_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216865151	73720	0	0
T15	24403	0	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T40	522167	5782	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T143	0	8292	0	0
T182	0	4940	0	0
T185	0	2540	0	0
T186	0	1971	0	0
T187	0	5319	0	0
T188	0	1771	0	0
T189	0	7101	0	0
T190	0	3752	0	0
T191	0	2923	0	0

ctrl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216865151	65028	0	0
T12	4198	0	0	0
T15	24403	0	0	0
T21	2959	0	0	0
T23	0	8	0	0
T24	0	5	0	0
T40	522167	5476	0	0
T44	2755	0	0	0
T51	29252	11	0	0
T57	1142	0	0	0
T60	1369	0	0	0
T61	1474	0	0	0
T63	2474	0	0	0
T101	0	6	0	0
T143	0	7290	0	0
T182	0	4168	0	0
T185	0	2066	0	0
T186	0	1677	0	0
T192	0	4	0	0

err_code_test_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216865151	75192	0	0
T15	24403	0	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T40	522167	6175	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T143	0	8447	0	0
T182	0	4996	0	0
T185	0	2436	0	0
T186	0	1721	0	0
T187	0	5404	0	0
T188	0	1946	0	0
T189	0	7370	0	0
T190	0	3767	0	0
T191	0	2875	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216865151	71952	0	0
T12	4198	0	0	0
T15	24403	0	0	0
T21	2959	0	0	0
T40	522167	5547	0	0
T44	2755	0	0	0
T51	29252	45	0	0
T57	1142	0	0	0
T60	1369	0	0	0
T61	1474	0	0	0
T63	2474	0	0	0
T143	0	7498	0	0
T182	0	4659	0	0
T185	0	2229	0	0
T186	0	2014	0	0
T193	0	27	0	0
T194	0	13	0	0
T195	0	79	0	0
T196	0	25	0	0

max_num_reqs_between_reseeds_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216865151	65528	0	0
T15	24403	0	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T40	522167	5525	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T143	0	7216	0	0
T182	0	4120	0	0
T185	0	1974	0	0
T186	0	1655	0	0
T187	0	4523	0	0
T188	0	1627	0	0
T189	0	6337	0	0
T190	0	3250	0	0
T191	0	2633	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	216865151	74550	0	0
T15	24403	0	0	0
T21	2959	0	0	0
T28	838	0	0	0
T35	1787	0	0	0
T40	522167	6064	0	0
T41	126339	0	0	0
T42	245448	0	0	0
T43	9012	0	0	0
T48	2215	0	0	0
T57	1142	0	0	0
T143	0	8394	0	0
T182	0	5292	0	0
T185	0	2499	0	0
T186	0	2032	0	0
T187	0	5040	0	0
T188	0	1825	0	0
T189	0	6814	0	0
T190	0	3689	0	0
T191	0	2787	0	0